mirror of
https://github.com/brain-hackers/u-boot-brain
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4549e789c1
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have multiple licenses (in these cases, dual license) declared in the SPDX-License-Identifier tag. In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B" as per the Linux Kernel style document. Note that parenthesis are allowed so when they were used before we continue to use them. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
288 lines
7.3 KiB
Plaintext
288 lines
7.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Device Tree Include file for Freescale Layerscape-1046A family SoC.
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*
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* Copyright (C) 2016, Freescale Semiconductor
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*
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* Mingkai Hu <mingkai.hu@nxp.com>
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*/
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/include/ "skeleton64.dtsi"
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/ {
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compatible = "fsl,ls1046a";
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interrupt-parent = <&gic>;
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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gic: interrupt-controller@1400000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x1410000 0 0x10000>, /* GICD */
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<0x0 0x1420000 0 0x10000>, /* GICC */
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<0x0 0x1440000 0 0x20000>, /* GICH */
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<0x0 0x1460000 0 0x20000>; /* GICV */
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interrupts = <1 9 0xf08>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clockgen: clocking@1ee1000 {
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compatible = "fsl,ls1046a-clockgen";
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reg = <0x0 0x1ee1000 0x0 0x1000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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dspi0: dspi@2100000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <0 64 0x4>;
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clock-names = "dspi";
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clocks = <&clockgen 4 0>;
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num-cs = <6>;
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big-endian;
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status = "disabled";
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};
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dspi1: dspi@2110000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2110000 0x0 0x10000>;
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interrupts = <0 65 0x4>;
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clock-names = "dspi";
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clocks = <&clockgen 4 0>;
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num-cs = <6>;
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big-endian;
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status = "disabled";
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};
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ifc: ifc@1530000 {
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compatible = "fsl,ifc", "simple-bus";
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reg = <0x0 0x1530000 0x0 0x10000>;
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interrupts = <0 43 0x4>;
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};
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i2c0: i2c@2180000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2180000 0x0 0x10000>;
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interrupts = <0 56 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c1: i2c@2190000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2190000 0x0 0x10000>;
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interrupts = <0 57 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c2: i2c@21a0000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x21a0000 0x0 0x10000>;
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interrupts = <0 58 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c3: i2c@21b0000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x21b0000 0x0 0x10000>;
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interrupts = <0 59 0x4>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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duart0: serial@21c0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x00 0x21c0500 0x0 0x100>;
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interrupts = <0 54 0x4>;
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clocks = <&clockgen 4 0>;
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};
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duart1: serial@21c0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x00 0x21c0600 0x0 0x100>;
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interrupts = <0 54 0x4>;
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clocks = <&clockgen 4 0>;
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};
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duart2: serial@21d0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21d0500 0x0 0x100>;
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interrupts = <0 55 0x4>;
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clocks = <&clockgen 4 0>;
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};
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duart3: serial@21d0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21d0600 0x0 0x100>;
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interrupts = <0 55 0x4>;
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clocks = <&clockgen 4 0>;
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};
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lpuart0: serial@2950000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2950000 0x0 0x1000>;
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interrupts = <0 48 0x4>;
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clocks = <&clockgen 4 0>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart1: serial@2960000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2960000 0x0 0x1000>;
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interrupts = <0 49 0x4>;
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clocks = <&clockgen 4 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart2: serial@2970000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2970000 0x0 0x1000>;
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interrupts = <0 50 0x4>;
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clocks = <&clockgen 4 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart3: serial@2980000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2980000 0x0 0x1000>;
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interrupts = <0 51 0x4>;
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clocks = <&clockgen 4 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart4: serial@2990000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2990000 0x0 0x1000>;
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interrupts = <0 52 0x4>;
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clocks = <&clockgen 4 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart5: serial@29a0000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x29a0000 0x0 0x1000>;
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interrupts = <0 53 0x4>;
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clocks = <&clockgen 4 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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qspi: quadspi@1550000 {
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compatible = "fsl,vf610-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x1550000 0x0 0x10000>,
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<0x0 0x40000000 0x0 0x10000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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num-cs = <4>;
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big-endian;
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status = "disabled";
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};
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usb0: usb@2f00000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x2f00000 0x0 0x10000>;
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interrupts = <0 60 4>;
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dr_mode = "host";
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};
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usb1: usb@3000000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3000000 0x0 0x10000>;
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interrupts = <0 61 4>;
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dr_mode = "host";
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};
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usb2: usb@3100000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3100000 0x0 0x10000>;
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interrupts = <0 63 4>;
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dr_mode = "host";
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};
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pcie@3400000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
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0x00 0x03480000 0x0 0x40000 /* lut registers */
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0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
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0x40 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "ctrl", "config";
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big-endian;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie@3500000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
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0x00 0x03580000 0x0 0x40000 /* lut registers */
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0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
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0x48 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "ctrl", "config";
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big-endian;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <2>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie@3600000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
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0x00 0x03680000 0x0 0x40000 /* lut registers */
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0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
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0x50 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "ctrl", "config";
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big-endian;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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};
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};
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