mirror of
https://github.com/brain-hackers/u-boot-brain
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c5ba6357b3
The whole cache code needs to be redesign to read information about cache from DT instead of macro selection. Enable caches by default because systems have caches on by default for Linux. Also enable CMD_CACHE to be able to disable cache if there is any issue. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
197 lines
5.0 KiB
C
197 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007-2010 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "../board/xilinx/microblaze-generic/xparameters.h"
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/* MicroBlaze CPU */
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#define MICROBLAZE_V5 1
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/* linear and spi flash memory */
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#ifdef XILINX_FLASH_START
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#define FLASH
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#undef SPIFLASH
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#undef RAMENV /* hold environment in flash */
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#else
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#undef FLASH
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#undef SPIFLASH
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#define RAMENV /* hold environment in RAM */
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#endif
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/* uart */
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/* The following table includes the supported baudrates */
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# define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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/* setting reset address */
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/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
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#define CONFIG_SYS_MALLOC_LEN 0xC0000
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/* Stack location before relocation */
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
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CONFIG_SYS_MALLOC_F_LEN)
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/*
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* CFI flash memory layout - Example
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* CONFIG_SYS_FLASH_BASE = 0x2200_0000;
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* CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
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*
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* SECT_SIZE = 0x20000; 128kB is one sector
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* CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
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*
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* 0x2200_0000 CONFIG_SYS_FLASH_BASE
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* FREE 256kB
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* 0x2204_0000 CONFIG_ENV_ADDR
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* ENV_AREA 128kB
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* 0x2206_0000
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* FREE
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* 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
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*
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*/
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#ifdef FLASH
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# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
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# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
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/* ?empty sector */
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# define CONFIG_SYS_FLASH_EMPTY_INFO 1
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/* max number of memory banks */
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# define CONFIG_SYS_MAX_FLASH_BANKS 1
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/* max number of sectors on one chip */
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# define CONFIG_SYS_MAX_FLASH_SECT 512
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/* hardware flash protection */
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/* use buffered writes (20x faster) */
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# ifdef RAMENV
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# define CONFIG_ENV_SIZE 0x1000
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# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
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# else /* FLASH && !RAMENV */
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/* 128K(one sector) for env */
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# define CONFIG_ENV_SECT_SIZE 0x20000
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# define CONFIG_ENV_ADDR \
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(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
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# define CONFIG_ENV_SIZE 0x20000
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# endif /* FLASH && !RAMBOOT */
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#else /* !FLASH */
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#ifdef SPIFLASH
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# ifdef RAMENV
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# define CONFIG_ENV_SIZE 0x1000
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# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
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# else /* SPIFLASH && !RAMENV */
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/* 128K(two sectors) for env */
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# define CONFIG_ENV_SECT_SIZE 0x10000
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# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
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/* Warning: adjust the offset in respect of other flash content and size */
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# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
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# endif /* SPIFLASH && !RAMBOOT */
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#else /* !SPIFLASH */
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/* ENV in RAM */
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# define CONFIG_ENV_SIZE 0x1000
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# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
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#endif /* !SPIFLASH */
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#endif /* !FLASH */
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#define XILINX_USE_ICACHE 1
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#define XILINX_USE_DCACHE 1
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#if defined(XILINX_USE_ICACHE)
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# define CONFIG_ICACHE
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#else
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# undef CONFIG_ICACHE
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#endif
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#if defined(XILINX_USE_DCACHE)
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# define CONFIG_DCACHE
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#else
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# undef CONFIG_DCACHE
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#endif
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#ifndef XILINX_DCACHE_BYTE_SIZE
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#define XILINX_DCACHE_BYTE_SIZE 32768
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#if defined(CONFIG_MTD_PARTITIONS)
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/* MTD partitions */
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/* default mtd partition table */
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#endif
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/* size of console buffer */
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#define CONFIG_SYS_CBSIZE 512
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/* max number of command args */
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#define CONFIG_SYS_MAXARGS 15
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0
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#define CONFIG_HOSTNAME "microblaze-generic"
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#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
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/* architecture dependent code */
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#define CONFIG_SYS_USR_EXCEP /* user exception */
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#ifndef CONFIG_EXTRA_ENV_SETTINGS
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#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
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"nor0=flash-0\0"\
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"mtdparts=mtdparts=flash-0:"\
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"256k(u-boot),256k(env),3m(kernel),"\
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"1m(romfs),1m(cramfs),-(jffs2)\0"\
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"nc=setenv stdout nc;"\
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"setenv stdin nc\0" \
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"serial=setenv stdout serial;"\
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"setenv stdin serial\0"
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#endif
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#if defined(CONFIG_XILINX_AXIEMAC)
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# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
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#endif
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/* SPL part */
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#ifdef CONFIG_SYS_FLASH_BASE
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# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
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#endif
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/* for booting directly linux */
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#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
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0x40000)
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#define CONFIG_SYS_FDT_SIZE (16 << 10)
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#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
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0x1000000)
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/* SP location before relocation, must use scratch RAM */
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/* BRAM start */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x0
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/* BRAM size - will be generated */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
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# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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CONFIG_SYS_MALLOC_F_LEN)
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/* Just for sure that there is a space for stack */
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#define CONFIG_SPL_STACK_SIZE 0x100
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#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
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CONFIG_SYS_INIT_RAM_ADDR - \
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CONFIG_SYS_MALLOC_F_LEN - \
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CONFIG_SPL_STACK_SIZE)
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#endif /* __CONFIG_H */
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