mirror of
https://github.com/brain-hackers/u-boot-brain
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ca831f4933
A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
63 lines
1.2 KiB
C
63 lines
1.2 KiB
C
/*
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* Copyright (c) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <pch.h>
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#include <dm/root.h>
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DECLARE_GLOBAL_DATA_PTR;
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int pch_get_sbase(struct udevice *dev, ulong *sbasep)
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{
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struct pch_ops *ops = pch_get_ops(dev);
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*sbasep = 0;
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if (!ops->get_sbase)
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return -ENOSYS;
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return ops->get_sbase(dev, sbasep);
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}
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enum pch_version pch_get_version(struct udevice *dev)
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{
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struct pch_ops *ops = pch_get_ops(dev);
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if (!ops->get_version)
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return -ENOSYS;
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return ops->get_version(dev);
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}
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int pch_set_spi_protect(struct udevice *dev, bool protect)
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{
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struct pch_ops *ops = pch_get_ops(dev);
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if (!ops->set_spi_protect)
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return -ENOSYS;
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return ops->set_spi_protect(dev, protect);
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}
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static int pch_uclass_post_bind(struct udevice *bus)
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{
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/*
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* Scan the device tree for devices
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*
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* Before relocation, only bind devices marked for pre-relocation
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* use.
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*/
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return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
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gd->flags & GD_FLG_RELOC ? false : true);
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}
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UCLASS_DRIVER(pch) = {
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.id = UCLASS_PCH,
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.name = "pch",
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.post_bind = pch_uclass_post_bind,
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};
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