mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-18 16:08:53 +09:00
![Benjamin Gaignard](/assets/img/avatar_default.png)
Implement hardware spinlock support for STM32MP1. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
1013 lines
22 KiB
Plaintext
1013 lines
22 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
|
/*
|
|
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
|
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
|
*/
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/clock/stm32mp1-clks.h>
|
|
#include <dt-bindings/reset/stm32mp1-resets.h>
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@0 {
|
|
compatible = "arm,cortex-a7";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
compatible = "arm,cortex-a7";
|
|
device_type = "cpu";
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci";
|
|
method = "smc";
|
|
cpu_off = <0x84000002>;
|
|
cpu_on = <0x84000003>;
|
|
};
|
|
|
|
aliases {
|
|
gpio0 = &gpioa;
|
|
gpio1 = &gpiob;
|
|
gpio2 = &gpioc;
|
|
gpio3 = &gpiod;
|
|
gpio4 = &gpioe;
|
|
gpio5 = &gpiof;
|
|
gpio6 = &gpiog;
|
|
gpio7 = &gpioh;
|
|
gpio8 = &gpioi;
|
|
gpio9 = &gpioj;
|
|
gpio10 = &gpiok;
|
|
serial0 = &usart1;
|
|
serial1 = &usart2;
|
|
serial2 = &usart3;
|
|
serial3 = &uart4;
|
|
serial4 = &uart5;
|
|
serial5 = &usart6;
|
|
serial6 = &uart7;
|
|
serial7 = &uart8;
|
|
};
|
|
|
|
intc: interrupt-controller@a0021000 {
|
|
compatible = "arm,cortex-a7-gic";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
reg = <0xa0021000 0x1000>,
|
|
<0xa0022000 0x2000>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
interrupt-parent = <&intc>;
|
|
};
|
|
|
|
clocks {
|
|
clk_hse: clk-hse {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
};
|
|
|
|
clk_hsi: clk-hsi {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <64000000>;
|
|
};
|
|
|
|
clk_lse: clk-lse {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
clk_lsi: clk-lsi {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
};
|
|
|
|
clk_csi: clk-csi {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <4000000>;
|
|
};
|
|
};
|
|
|
|
pm_domain {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32mp157c-pd";
|
|
|
|
pd_core_ret: core-ret-power-domain@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
#power-domain-cells = <0>;
|
|
label = "CORE-RETENTION";
|
|
|
|
pd_core: core-power-domain@2 {
|
|
reg = <2>;
|
|
#power-domain-cells = <0>;
|
|
label = "CORE";
|
|
};
|
|
};
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-parent = <&intc>;
|
|
ranges;
|
|
|
|
timers2: timer@40000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40000000 0x400>;
|
|
clocks = <&rcc TIM2_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@1 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers3: timer@40001000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40001000 0x400>;
|
|
clocks = <&rcc TIM3_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@2 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers4: timer@40002000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40002000 0x400>;
|
|
clocks = <&rcc TIM4_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@3 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers5: timer@40003000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40003000 0x400>;
|
|
clocks = <&rcc TIM5_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@4 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <4>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers6: timer@40004000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40004000 0x400>;
|
|
clocks = <&rcc TIM6_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
timer@5 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <5>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers7: timer@40005000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40005000 0x400>;
|
|
clocks = <&rcc TIM7_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
timer@6 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <6>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers12: timer@40006000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40006000 0x400>;
|
|
clocks = <&rcc TIM12_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@11 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <11>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers13: timer@40007000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40007000 0x400>;
|
|
clocks = <&rcc TIM13_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@12 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers14: timer@40008000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40008000 0x400>;
|
|
clocks = <&rcc TIM14_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@13 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <13>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
lptimer1: timer@40009000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-lptimer";
|
|
reg = <0x40009000 0x400>;
|
|
clocks = <&rcc LPTIM1_K>;
|
|
clock-names = "mux";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm-lp";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
trigger@0 {
|
|
compatible = "st,stm32-lptimer-trigger";
|
|
reg = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-lptimer-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usart2: serial@4000e000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x4000e000 0x400>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc USART2_K>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usart3: serial@4000f000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x4000f000 0x400>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc USART3_K>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@40010000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x40010000 0x400>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc UART4_K>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@40011000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x40011000 0x400>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc UART5_K>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@40012000 {
|
|
compatible = "st,stm32f7-i2c";
|
|
reg = <0x40012000 0x400>;
|
|
interrupt-names = "event", "error";
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc I2C1_K>;
|
|
resets = <&rcc I2C1_R>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@40013000 {
|
|
compatible = "st,stm32f7-i2c";
|
|
reg = <0x40013000 0x400>;
|
|
interrupt-names = "event", "error";
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc I2C2_K>;
|
|
resets = <&rcc I2C2_R>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@40014000 {
|
|
compatible = "st,stm32f7-i2c";
|
|
reg = <0x40014000 0x400>;
|
|
interrupt-names = "event", "error";
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc I2C3_K>;
|
|
resets = <&rcc I2C3_R>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@40015000 {
|
|
compatible = "st,stm32f7-i2c";
|
|
reg = <0x40015000 0x400>;
|
|
interrupt-names = "event", "error";
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc I2C5_K>;
|
|
resets = <&rcc I2C5_R>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cec: cec@40016000 {
|
|
compatible = "st,stm32-cec";
|
|
reg = <0x40016000 0x400>;
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc CEC_K>, <&clk_lse>;
|
|
clock-names = "cec", "hdmi-cec";
|
|
status = "disabled";
|
|
};
|
|
|
|
dac: dac@40017000 {
|
|
compatible = "st,stm32h7-dac-core";
|
|
reg = <0x40017000 0x400>;
|
|
clocks = <&rcc DAC12>;
|
|
clock-names = "pclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
dac1: dac@1 {
|
|
compatible = "st,stm32-dac";
|
|
#io-channels-cells = <1>;
|
|
reg = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dac2: dac@2 {
|
|
compatible = "st,stm32-dac";
|
|
#io-channels-cells = <1>;
|
|
reg = <2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
uart7: serial@40018000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x40018000 0x400>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc UART7_K>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart8: serial@40019000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x40019000 0x400>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc UART8_K>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timers1: timer@44000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x44000000 0x400>;
|
|
clocks = <&rcc TIM1_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@0 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers8: timer@44001000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x44001000 0x400>;
|
|
clocks = <&rcc TIM8_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@7 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <7>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usart6: serial@44003000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x44003000 0x400>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc USART6_K>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timers15: timer@44006000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x44006000 0x400>;
|
|
clocks = <&rcc TIM15_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@14 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <14>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers16: timer@44007000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x44007000 0x400>;
|
|
clocks = <&rcc TIM16_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
timer@15 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <15>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers17: timer@44008000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x44008000 0x400>;
|
|
clocks = <&rcc TIM17_K>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@16 {
|
|
compatible = "st,stm32h7-timer-trigger";
|
|
reg = <16>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
dma1: dma@48000000 {
|
|
compatible = "st,stm32-dma";
|
|
reg = <0x48000000 0x400>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc DMA1>;
|
|
#dma-cells = <4>;
|
|
st,mem2mem;
|
|
dma-requests = <8>;
|
|
};
|
|
|
|
dma2: dma@48001000 {
|
|
compatible = "st,stm32-dma";
|
|
reg = <0x48001000 0x400>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc DMA2>;
|
|
#dma-cells = <4>;
|
|
st,mem2mem;
|
|
dma-requests = <8>;
|
|
};
|
|
|
|
dmamux1: dma-router@48002000 {
|
|
compatible = "st,stm32h7-dmamux";
|
|
reg = <0x48002000 0x1c>;
|
|
#dma-cells = <3>;
|
|
dma-requests = <128>;
|
|
dma-masters = <&dma1 &dma2>;
|
|
dma-channels = <16>;
|
|
clocks = <&rcc DMAMUX>;
|
|
};
|
|
|
|
adc: adc@48003000 {
|
|
compatible = "st,stm32mp1-adc-core";
|
|
reg = <0x48003000 0x400>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc ADC12>, <&rcc ADC12_K>;
|
|
clock-names = "bus", "adc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
adc1: adc@0 {
|
|
compatible = "st,stm32mp1-adc";
|
|
#io-channel-cells = <1>;
|
|
reg = <0x0>;
|
|
interrupt-parent = <&adc>;
|
|
interrupts = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc2: adc@100 {
|
|
compatible = "st,stm32mp1-adc";
|
|
#io-channel-cells = <1>;
|
|
reg = <0x100>;
|
|
interrupt-parent = <&adc>;
|
|
interrupts = <1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
sdmmc3: sdmmc@48004000 {
|
|
compatible = "st,stm32-sdmmc2";
|
|
reg = <0x48004000 0x400>, <0x48005000 0x400>;
|
|
reg-names = "sdmmc", "delay";
|
|
interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
|
|
clocks = <&rcc SDMMC3_K>;
|
|
resets = <&rcc SDMMC3_R>;
|
|
st,idma = <1>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
max-frequency = <120000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg_hs: usb-otg@49000000 {
|
|
compatible = "st,stm32mp1-hsotg", "snps,dwc2";
|
|
reg = <0x49000000 0x10000>;
|
|
clocks = <&rcc USBO_K>;
|
|
clock-names = "otg";
|
|
resets = <&rcc USBO_R>;
|
|
reset-names = "dwc2";
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
g-rx-fifo-size = <256>;
|
|
g-np-tx-fifo-size = <32>;
|
|
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
|
|
dr_mode = "otg";
|
|
power-domains = <&pd_core>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hwspinlock: hwspinlock@4c000000 {
|
|
compatible = "st,stm32-hwspinlock";
|
|
#hwlock-cells = <1>;
|
|
reg = <0x4c000000 0x400>;
|
|
clocks = <&rcc HSEM>;
|
|
clock-names = "hwspinlock";
|
|
status = "disabled";
|
|
};
|
|
|
|
rcc: rcc@50000000 {
|
|
compatible = "st,stm32mp1-rcc", "syscon";
|
|
reg = <0x50000000 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
rcc_reboot: rcc-reboot@50000000 {
|
|
compatible = "syscon-reboot";
|
|
regmap = <&rcc>;
|
|
offset = <0x404>;
|
|
mask = <0x1>;
|
|
};
|
|
|
|
pwr: pwr@50001000 {
|
|
compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd";
|
|
reg = <0x50001000 0x400>;
|
|
system-power-controller;
|
|
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
st,sysrcc = <&rcc>;
|
|
clocks = <&rcc PLL2_R>;
|
|
clock-names = "phyclk";
|
|
|
|
pwr-regulators@c {
|
|
compatible = "st,stm32mp1,pwr-reg";
|
|
st,tzcr = <&rcc 0x0 0x1>;
|
|
|
|
reg11: reg11 {
|
|
regulator-name = "reg11";
|
|
regulator-min-microvolt = <1100000>;
|
|
regulator-max-microvolt = <1100000>;
|
|
};
|
|
|
|
reg18: reg18 {
|
|
regulator-name = "reg18";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
usb33: usb33 {
|
|
regulator-name = "usb33";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
exti: interrupt-controller@5000d000 {
|
|
compatible = "st,stm32mp1-exti", "syscon";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x5000d000 0x400>;
|
|
};
|
|
|
|
syscfg: system-config@50020000 {
|
|
compatible = "st,stm32-syscfg", "syscon";
|
|
reg = <0x50020000 0x400>;
|
|
};
|
|
|
|
lptimer2: timer@50021000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-lptimer";
|
|
reg = <0x50021000 0x400>;
|
|
clocks = <&rcc LPTIM2_K>;
|
|
clock-names = "mux";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm-lp";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
trigger@1 {
|
|
compatible = "st,stm32-lptimer-trigger";
|
|
reg = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-lptimer-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
lptimer3: timer@50022000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-lptimer";
|
|
reg = <0x50022000 0x400>;
|
|
clocks = <&rcc LPTIM3_K>;
|
|
clock-names = "mux";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm-lp";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
trigger@2 {
|
|
compatible = "st,stm32-lptimer-trigger";
|
|
reg = <2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
lptimer4: timer@50023000 {
|
|
compatible = "st,stm32-lptimer";
|
|
reg = <0x50023000 0x400>;
|
|
clocks = <&rcc LPTIM4_K>;
|
|
clock-names = "mux";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm-lp";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
lptimer5: timer@50024000 {
|
|
compatible = "st,stm32-lptimer";
|
|
reg = <0x50024000 0x400>;
|
|
clocks = <&rcc LPTIM5_K>;
|
|
clock-names = "mux";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm-lp";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
vrefbuf: vrefbuf@50025000 {
|
|
compatible = "st,stm32-vrefbuf";
|
|
reg = <0x50025000 0x8>;
|
|
regulator-min-microvolt = <1500000>;
|
|
regulator-max-microvolt = <2500000>;
|
|
clocks = <&rcc VREF>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cryp1: cryp@54001000 {
|
|
compatible = "st,stm32mp1-cryp";
|
|
reg = <0x54001000 0x400>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc CRYP1>;
|
|
resets = <&rcc CRYP1_R>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rng1: rng@54003000 {
|
|
compatible = "st,stm32-rng";
|
|
reg = <0x54003000 0x400>;
|
|
clocks = <&rcc RNG1_K>;
|
|
resets = <&rcc RNG1_R>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mdma1: dma@58000000 {
|
|
compatible = "st,stm32h7-mdma";
|
|
reg = <0x58000000 0x1000>;
|
|
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc MDMA>;
|
|
#dma-cells = <5>;
|
|
dma-channels = <32>;
|
|
dma-requests = <48>;
|
|
};
|
|
|
|
qspi: qspi@58003000 {
|
|
compatible = "st,stm32f469-qspi";
|
|
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
|
reg-names = "qspi", "qspi_mm";
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc QSPI_K>;
|
|
resets = <&rcc QSPI_R>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdmmc1: sdmmc@58005000 {
|
|
compatible = "st,stm32-sdmmc2";
|
|
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
|
|
reg-names = "sdmmc", "delay";
|
|
clocks = <&rcc SDMMC1_K>;
|
|
resets = <&rcc SDMMC1_R>;
|
|
st,idma = <1>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
max-frequency = <120000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdmmc2: sdmmc@58007000 {
|
|
compatible = "st,stm32-sdmmc2";
|
|
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
|
|
reg-names = "sdmmc", "delay";
|
|
interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
|
|
clocks = <&rcc SDMMC2_K>;
|
|
resets = <&rcc SDMMC2_R>;
|
|
st,idma = <1>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
max-frequency = <120000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
crc1: crc@58009000 {
|
|
compatible = "st,stm32f7-crc";
|
|
reg = <0x58009000 0x400>;
|
|
clocks = <&rcc CRC1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh_ohci: usbh-ohci@5800c000 {
|
|
compatible = "generic-ohci";
|
|
reg = <0x5800c000 0x1000>;
|
|
clocks = <&rcc USBH>;
|
|
resets = <&rcc USBH_R>;
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh_ehci: usbh-ehci@5800d000 {
|
|
compatible = "generic-ehci";
|
|
reg = <0x5800d000 0x1000>;
|
|
clocks = <&rcc USBH>;
|
|
resets = <&rcc USBH_R>;
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
companion = <&usbh_ohci>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dsi: dsi@5a000000 {
|
|
compatible = "st,stm32-dsi";
|
|
reg = <0x5a000000 0x800>;
|
|
clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
|
|
clock-names = "pclk", "ref", "px_clk";
|
|
resets = <&rcc DSI_R>;
|
|
reset-names = "apb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ltdc: display-controller@5a001000 {
|
|
compatible = "st,stm32-ltdc";
|
|
reg = <0x5a001000 0x400>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc LTDC_PX>;
|
|
clock-names = "lcd";
|
|
resets = <&rcc LTDC_R>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbphyc: usbphyc@5a006000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32mp1-usbphyc";
|
|
reg = <0x5a006000 0x1000>;
|
|
clocks = <&rcc USBPHY_K>;
|
|
resets = <&rcc USBPHY_R>;
|
|
status = "disabled";
|
|
|
|
usbphyc_port0: usb-phy@0 {
|
|
#phy-cells = <0>;
|
|
reg = <0>;
|
|
};
|
|
|
|
usbphyc_port1: usb-phy@1 {
|
|
#phy-cells = <1>;
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
usart1: serial@5c000000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x5c000000 0x400>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc USART1_K>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@5c002000 {
|
|
compatible = "st,stm32f7-i2c";
|
|
reg = <0x5c002000 0x400>;
|
|
interrupt-names = "event", "error";
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc I2C4_K>;
|
|
resets = <&rcc I2C4_R>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@5c009000 {
|
|
compatible = "st,stm32f7-i2c";
|
|
reg = <0x5c009000 0x400>;
|
|
interrupt-names = "event", "error";
|
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc I2C6_K>;
|
|
resets = <&rcc I2C6_R>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|