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![Felipe Balbi](/assets/img/avatar_default.png)
Out of all OMAP5-like boards, only one of them needs CONFIG_MISC_INIT_R, so it's best to enable that for that particular board only, instead of enabling for all boards unconditionally. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
293 lines
6.9 KiB
C
293 lines
6.9 KiB
C
/*
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* (C) Copyright 2013
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* Lokesh Vutla <lokeshvutla@ti.com>
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*
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* Based on previous work by:
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* Aneesh V <aneesh@ti.com>
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* Steve Sakoman <steve@sakoman.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <palmas.h>
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#include <sata.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sata.h>
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#include <environment.h>
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#include "mux_data.h"
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#ifdef CONFIG_DRIVER_TI_CPSW
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#include <cpsw.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* GPIO 7_11 */
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#define GPIO_DDR_VTT_EN 203
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const struct omap_sysinfo sysinfo = {
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"Board: DRA7xx\n"
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};
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/*
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* Adjust I/O delays on the Tx control and data lines of each MAC port. This
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* is a workaround in order to work properly with the DP83865 PHYs on the EVM.
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* In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
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* essentially need to counteract the DRA7xx internal delay, and we do this
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* by delaying the control and data lines. If not using this PHY, you probably
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* don't need to do this stuff!
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*/
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static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
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{
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int i = 0;
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u32 reg_val;
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u32 delta;
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u32 coarse;
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u32 fine;
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writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
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while(io_dly[i].addr) {
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writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
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io_dly[i].addr);
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delta = io_dly[i].dly;
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reg_val = readl(io_dly[i].addr) & 0x3ff;
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coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
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coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
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fine = (reg_val & 0x1F) + (delta & 0x1F);
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fine = (fine > 0x1F) ? (0x1F) : (fine);
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reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
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CFG_IO_DELAY_LOCK_MASK |
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((coarse << 5) | (fine));
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writel(reg_val, io_dly[i].addr);
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i++;
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}
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writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
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}
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/**
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* @brief board_init
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*
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* @return 0
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*/
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int board_init(void)
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{
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gpmc_init();
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gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
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return 0;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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if (omap_revision() == DRA722_ES1_0)
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setenv("board_name", "dra72x");
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else
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setenv("board_name", "dra7xx");
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#endif
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return 0;
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}
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static void do_set_mux32(u32 base,
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struct pad_conf_entry const *array, int size)
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{
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int i;
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struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
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for (i = 0; i < size; i++, pad++)
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writel(pad->val, base + pad->offset);
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}
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void set_muxconf_regs_essential(void)
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{
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do_set_mux32((*ctrl)->control_padconf_core_base,
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core_padconf_array_essential,
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sizeof(core_padconf_array_essential) /
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sizeof(struct pad_conf_entry));
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}
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
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int board_mmc_init(bd_t *bis)
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{
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omap_mmc_init(0, 0, 0, -1, -1);
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omap_mmc_init(1, 0, 0, -1, -1);
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return 0;
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}
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#endif
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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#ifdef CONFIG_SPL_ENV_SUPPORT
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env_init();
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env_relocate_spec();
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if (getenv_yesno("boot_os") != 1)
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return 1;
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_DRIVER_TI_CPSW
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/* Delay value to add to calibrated value */
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#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
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#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
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#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
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#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
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#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
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#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
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#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
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#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
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#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
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#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
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extern u32 *const omap_si_rev;
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 2,
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},
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{
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.slave_reg_ofs = 0x308,
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.sliver_reg_ofs = 0xdc0,
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.phy_addr = 3,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 2,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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int board_eth_init(bd_t *bis)
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{
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int ret;
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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uint32_t ctrl_val;
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const struct io_delay io_dly[] = {
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{CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
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{CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
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{CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
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{CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
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{CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
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{CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
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{CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
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{CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
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{CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
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{CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
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{0}
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};
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/* Adjust IO delay for RGMII tx path */
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dra7xx_adj_io_delay(io_dly);
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/* try reading mac address from efuse */
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mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
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mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
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mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = mac_hi & 0xFF;
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mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
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mac_addr[4] = (mac_lo & 0xFF00) >> 8;
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mac_addr[5] = mac_lo & 0xFF;
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if (!getenv("ethaddr")) {
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printf("<ethaddr> not set. Validating first E-fuse MAC\n");
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if (is_valid_ether_addr(mac_addr))
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eth_setenv_enetaddr("ethaddr", mac_addr);
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}
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mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
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mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
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mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = mac_hi & 0xFF;
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mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
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mac_addr[4] = (mac_lo & 0xFF00) >> 8;
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mac_addr[5] = mac_lo & 0xFF;
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if (!getenv("eth1addr")) {
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if (is_valid_ether_addr(mac_addr))
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eth_setenv_enetaddr("eth1addr", mac_addr);
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}
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ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
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ctrl_val |= 0x22;
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writel(ctrl_val, (*ctrl)->control_core_control_io1);
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if (*omap_si_rev == DRA722_ES1_0)
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cpsw_data.active_slave = 1;
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ret = cpsw_register(&cpsw_data);
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if (ret < 0)
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printf("Error %d registering CPSW switch\n", ret);
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return ret;
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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/* VTT regulator enable */
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static inline void vtt_regulator_enable(void)
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{
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if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
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return;
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/* Do not enable VTT for DRA722 */
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if (omap_revision() == DRA722_ES1_0)
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return;
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/*
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* EVM Rev G and later use gpio7_11 for DDR3 termination.
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* This is safe enough to do on older revs.
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*/
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gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
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gpio_direction_output(GPIO_DDR_VTT_EN, 1);
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}
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int board_early_init_f(void)
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{
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vtt_regulator_enable();
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return 0;
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}
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#endif
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