mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
bfd092f9ca
Define board_late_init which performs bootmode detection and prepares corresponding distro boot commaand sequence. Also disable it for mini platforms because simply there is no need to have it enabled. But also disable it for virtual platform because Qemu is not modelling this register space that's why travis testing would fail. This configuration should be reverted when mainline Qemu is updated. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
77 lines
1.8 KiB
C
77 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016 - 2018 Xilinx, Inc.
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*/
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#define VERSAL_CRL_APB_BASEADDR 0xFF5E0000
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#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25)
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#define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25)
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#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
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struct crlapb_regs {
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u32 reserved0[67];
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u32 cpu_r5_ctrl;
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u32 reserved;
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u32 iou_switch_ctrl; /* 0x114 */
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u32 reserved1[13];
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u32 timestamp_ref_ctrl; /* 0x14c */
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u32 reserved3[108];
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u32 rst_cpu_r5;
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u32 reserved2[17];
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u32 rst_timestamp; /* 0x348 */
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};
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#define crlapb_base ((struct crlapb_regs *)VERSAL_CRL_APB_BASEADDR)
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#define VERSAL_IOU_SCNTR_SECURE 0xFF140000
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#define IOU_SCNTRS_CONTROL_EN 1
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struct iou_scntrs_regs {
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u32 counter_control_register; /* 0x0 */
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u32 reserved0[7];
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u32 base_frequency_id_register; /* 0x20 */
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};
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#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_IOU_SCNTR_SECURE)
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#define VERSAL_TCM_BASE_ADDR 0xFFE00000
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#define VERSAL_TCM_SIZE 0x40000
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#define VERSAL_RPU_BASEADDR 0xFF9A0000
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struct rpu_regs {
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u32 rpu_glbl_ctrl;
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u32 reserved0[63];
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u32 rpu0_cfg; /* 0x100 */
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u32 reserved1[63];
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u32 rpu1_cfg; /* 0x200 */
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};
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#define rpu_base ((struct rpu_regs *)VERSAL_RPU_BASEADDR)
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#define VERSAL_CRP_BASEADDR 0xF1260000
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struct crp_regs {
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u32 reserved0[128];
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u32 boot_mode_usr;
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};
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#define crp_base ((struct crp_regs *)VERSAL_CRP_BASEADDR)
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/* Bootmode setting values */
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#define BOOT_MODES_MASK 0x0000000F
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#define QSPI_MODE_24BIT 0x00000001
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#define QSPI_MODE_32BIT 0x00000002
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#define SD_MODE 0x00000003 /* sd 0 */
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#define SD_MODE1 0x00000005 /* sd 1 */
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#define EMMC_MODE 0x00000006
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#define USB_MODE 0x00000007
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#define OSPI_MODE 0x00000008
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#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
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#define JTAG_MODE 0x00000000
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#define BOOT_MODE_USE_ALT 0x100
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#define BOOT_MODE_ALT_SHIFT 12
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