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https://github.com/brain-hackers/u-boot-brain
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3723549695
This patch adds support for the LaCie boards Network Space v2 (Lite and Mini). This two boards are derived from the Network Space v2 and a lot of hardware caracteristics are shared. - CPU: Marvell 88F6192 800Mhz - SDRAM memory: 128MB DDR2 200Mhz - 1 SATA port: internal - Gigabit ethernet: PHY Marvell 88E1318 - Flash memory: SPI NOR 512KB (Macronix MX25L4005A) - i2c EEPROM: 512 bytes (24C04 type) - 2 USB2 ports (Lite only): host and host/device - 1 push button - 1 SATA LED (bi-color, blue and red) Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
109 lines
3.0 KiB
C
109 lines
3.0 KiB
C
/*
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* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <miiphy.h>
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
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#define MII_MARVELL_PHY_PAGE 22
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#define MV88E1116_LED_FCTRL_REG 10
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#define MV88E1116_CPRSP_CR3_REG 21
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#define MV88E1116_MAC_CTRL_REG 21
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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void mv_phy_88e1116_init(const char *name, u16 phyaddr)
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{
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u16 reg;
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if (miiphy_set_current_dev(name))
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return;
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
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miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
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if (miiphy_reset(name, phyaddr) == 0)
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printf("88E1116 Initialized on %s\n", name);
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}
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void mv_phy_88e1318_init(const char *name, u16 phyaddr)
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{
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u16 reg;
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if (miiphy_set_current_dev(name))
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return;
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/*
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* Set control mode 4 for LED[0].
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*/
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
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miiphy_read(name, phyaddr, 16, ®);
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reg |= 0xf;
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miiphy_write(name, phyaddr, 16, reg);
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
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miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
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miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
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if (miiphy_reset(name, phyaddr) == 0)
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printf("88E1318 Initialized on %s\n", name);
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}
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#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
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#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
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int lacie_read_mac_address(uchar *mac_addr)
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{
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int ret;
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ushort version;
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/* I2C-0 for on-board EEPROM */
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i2c_set_bus_num(0);
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/* Check layout version for EEPROM data */
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ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
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(uchar *) &version, 2);
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if (ret != 0) {
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printf("Error: failed to read I2C EEPROM @%02x\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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return ret;
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}
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version = be16_to_cpu(version);
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if (version < 1 || version > 3) {
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printf("Error: unknown version %d for EEPROM data\n",
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version);
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return -1;
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}
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/* Read Ethernet MAC address from EEPROM */
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ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6);
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if (ret != 0)
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printf("Error: failed to read I2C EEPROM @%02x\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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return ret;
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}
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#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */
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