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![Kever Yang](/assets/img/avatar_default.png)
Init CPU frquency in clock driver instead of in SPL board file, this will help for use common board file later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
620 lines
16 KiB
C
620 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2015 Google, Inc
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* (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <errno.h>
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#include <mapmem.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru_rk3188.h>
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#include <asm/arch-rockchip/grf_rk3188.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <dt-bindings/clock/rk3188-cru.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/uclass-internal.h>
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#include <linux/log2.h>
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enum rk3188_clk_type {
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RK3188_CRU,
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RK3188A_CRU,
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};
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struct rk3188_clk_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3188_cru dtd;
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#endif
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};
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struct pll_div {
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u32 nr;
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u32 nf;
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u32 no;
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};
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enum {
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VCO_MAX_HZ = 2200U * 1000000,
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VCO_MIN_HZ = 440 * 1000000,
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OUTPUT_MAX_HZ = 2200U * 1000000,
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OUTPUT_MIN_HZ = 30 * 1000000,
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FREF_MAX_HZ = 2200U * 1000000,
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FREF_MIN_HZ = 30 * 1000,
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};
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enum {
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/* PLL CON0 */
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PLL_OD_MASK = 0x0f,
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/* PLL CON1 */
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PLL_NF_MASK = 0x1fff,
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/* PLL CON2 */
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PLL_BWADJ_MASK = 0x0fff,
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/* PLL CON3 */
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PLL_RESET_SHIFT = 5,
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/* GRF_SOC_STATUS0 */
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SOCSTS_DPLL_LOCK = 1 << 5,
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SOCSTS_APLL_LOCK = 1 << 6,
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SOCSTS_CPLL_LOCK = 1 << 7,
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SOCSTS_GPLL_LOCK = 1 << 8,
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};
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#define PLL_DIVISORS(hz, _nr, _no) {\
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.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
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_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
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(_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
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"divisors on line " __stringify(__LINE__));
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/* Keep divisors as low as possible to reduce jitter and power usage */
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#ifdef CONFIG_SPL_BUILD
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
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static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
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#endif
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static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id,
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const struct pll_div *div, bool has_bwadj)
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{
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int pll_id = rk_pll_id(clk_id);
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struct rk3188_pll *pll = &cru->pll[pll_id];
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/* All PLLs have same VCO and output frequency range restrictions. */
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uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
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uint output_hz = vco_hz / div->no;
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debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
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(uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
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(div->no == 1 || !(div->no % 2)));
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/* enter reset */
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rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
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rk_clrsetreg(&pll->con0,
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CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
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((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
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rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
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if (has_bwadj)
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rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
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udelay(10);
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/* return from reset */
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rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
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return 0;
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}
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static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf,
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unsigned int hz, bool has_bwadj)
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{
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static const struct pll_div dpll_cfg[] = {
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{.nf = 75, .nr = 1, .no = 6},
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{.nf = 400, .nr = 9, .no = 2},
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{.nf = 500, .nr = 9, .no = 2},
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{.nf = 100, .nr = 3, .no = 1},
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};
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int cfg;
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switch (hz) {
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case 300000000:
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cfg = 0;
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break;
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case 533000000: /* actually 533.3P MHz */
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cfg = 1;
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break;
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case 666000000: /* actually 666.6P MHz */
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cfg = 2;
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break;
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case 800000000:
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cfg = 3;
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break;
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default:
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debug("Unsupported SDRAM frequency");
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return -EINVAL;
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}
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/* pll enter slow-mode */
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rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
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DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
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rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);
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/* wait for pll lock */
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while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
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udelay(1);
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/* PLL enter normal-mode */
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rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
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DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
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return 0;
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}
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static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf,
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unsigned int hz, bool has_bwadj)
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{
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static const struct pll_div apll_cfg[] = {
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{.nf = 50, .nr = 1, .no = 2},
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{.nf = 67, .nr = 1, .no = 1},
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};
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int div_core_peri, div_aclk_core, cfg;
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/*
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* We support two possible frequencies, the safe 600MHz
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* which will work with default pmic settings and will
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* be set in SPL to get away from the 24MHz default and
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* the maximum of 1.6Ghz, which boards can set if they
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* were able to get pmic support for it.
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*/
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switch (hz) {
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case APLL_SAFE_HZ:
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cfg = 0;
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div_core_peri = 1;
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div_aclk_core = 3;
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break;
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case APLL_HZ:
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cfg = 1;
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div_core_peri = 2;
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div_aclk_core = 3;
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break;
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default:
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debug("Unsupported ARMCLK frequency");
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return -EINVAL;
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}
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/* pll enter slow-mode */
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rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
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APLL_MODE_SLOW << APLL_MODE_SHIFT);
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rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);
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/* waiting for pll lock */
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while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
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udelay(1);
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/* Set divider for peripherals attached to the cpu core. */
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rk_clrsetreg(&cru->cru_clksel_con[0],
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CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
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div_core_peri << CORE_PERI_DIV_SHIFT);
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/* set up dependent divisor for aclk_core */
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rk_clrsetreg(&cru->cru_clksel_con[1],
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CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT,
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div_aclk_core << CORE_ACLK_DIV_SHIFT);
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/* PLL enter normal-mode */
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rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
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APLL_MODE_NORMAL << APLL_MODE_SHIFT);
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return hz;
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}
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/* Get pll rate by id */
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static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru,
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enum rk_clk_id clk_id)
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{
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uint32_t nr, no, nf;
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uint32_t con;
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int pll_id = rk_pll_id(clk_id);
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struct rk3188_pll *pll = &cru->pll[pll_id];
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static u8 clk_shift[CLK_COUNT] = {
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0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
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GPLL_MODE_SHIFT
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};
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uint shift;
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con = readl(&cru->cru_mode_con);
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shift = clk_shift[clk_id];
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switch ((con >> shift) & APLL_MODE_MASK) {
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case APLL_MODE_SLOW:
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return OSC_HZ;
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case APLL_MODE_NORMAL:
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/* normal mode */
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con = readl(&pll->con0);
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no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
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nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
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con = readl(&pll->con1);
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nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
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return (24 * nf / (nr * no)) * 1000000;
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case APLL_MODE_DEEP:
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default:
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return 32768;
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}
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}
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static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
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int periph)
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{
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uint div;
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u32 con;
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switch (periph) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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con = readl(&cru->cru_clksel_con[12]);
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div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
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break;
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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con = readl(&cru->cru_clksel_con[11]);
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div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
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break;
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case HCLK_SDIO:
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case SCLK_SDIO:
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con = readl(&cru->cru_clksel_con[12]);
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div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
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break;
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default:
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return -EINVAL;
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}
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return DIV_TO_RATE(gclk_rate, div) / 2;
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}
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static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
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int periph, uint freq)
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{
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int src_clk_div;
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debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
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/* mmc clock defaulg div 2 internal, need provide double in cru */
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src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
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assert(src_clk_div <= 0x3f);
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switch (periph) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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rk_clrsetreg(&cru->cru_clksel_con[12],
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EMMC_DIV_MASK << EMMC_DIV_SHIFT,
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src_clk_div << EMMC_DIV_SHIFT);
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break;
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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rk_clrsetreg(&cru->cru_clksel_con[11],
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MMC0_DIV_MASK << MMC0_DIV_SHIFT,
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src_clk_div << MMC0_DIV_SHIFT);
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break;
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case HCLK_SDIO:
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case SCLK_SDIO:
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rk_clrsetreg(&cru->cru_clksel_con[12],
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SDIO_DIV_MASK << SDIO_DIV_SHIFT,
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src_clk_div << SDIO_DIV_SHIFT);
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break;
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default:
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return -EINVAL;
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}
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return rockchip_mmc_get_clk(cru, gclk_rate, periph);
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}
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static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
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int periph)
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{
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uint div;
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u32 con;
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switch (periph) {
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case SCLK_SPI0:
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con = readl(&cru->cru_clksel_con[25]);
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div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
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break;
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case SCLK_SPI1:
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con = readl(&cru->cru_clksel_con[25]);
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div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
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break;
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default:
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return -EINVAL;
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}
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return DIV_TO_RATE(gclk_rate, div);
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}
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static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
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int periph, uint freq)
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{
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int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
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assert(src_clk_div < 128);
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switch (periph) {
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case SCLK_SPI0:
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assert(src_clk_div <= SPI0_DIV_MASK);
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rk_clrsetreg(&cru->cru_clksel_con[25],
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SPI0_DIV_MASK << SPI0_DIV_SHIFT,
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src_clk_div << SPI0_DIV_SHIFT);
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break;
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case SCLK_SPI1:
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assert(src_clk_div <= SPI1_DIV_MASK);
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rk_clrsetreg(&cru->cru_clksel_con[25],
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SPI1_DIV_MASK << SPI1_DIV_SHIFT,
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src_clk_div << SPI1_DIV_SHIFT);
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break;
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default:
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return -EINVAL;
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}
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return rockchip_spi_get_clk(cru, gclk_rate, periph);
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}
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#ifdef CONFIG_SPL_BUILD
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static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
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bool has_bwadj)
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{
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u32 aclk_div, hclk_div, pclk_div, h2p_div;
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/* pll enter slow-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK << GPLL_MODE_SHIFT |
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CPLL_MODE_MASK << CPLL_MODE_SHIFT,
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GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
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CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
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/* init pll */
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rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
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rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
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/* waiting for pll lock */
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while ((readl(&grf->soc_status0) &
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(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
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(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
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udelay(1);
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/*
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* cpu clock pll source selection and
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* reparent aclk_cpu_pre from apll to gpll
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1;
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assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
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A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT,
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CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
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aclk_div << A9_CPU_DIV_SHIFT);
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hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ);
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assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
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pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ);
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assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
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h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ);
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assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT |
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CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
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CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
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h2p_div << AHB2APB_DIV_SHIFT |
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pclk_div << CPU_PCLK_DIV_SHIFT |
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hclk_div << CPU_HCLK_DIV_SHIFT);
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/*
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* peri clock pll source selection and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
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assert((1 << hclk_div) * PERI_HCLK_HZ ==
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PERI_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
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assert((1 << pclk_div) * PERI_PCLK_HZ ==
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PERI_ACLK_HZ && (pclk_div < 0x4));
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rk_clrsetreg(&cru->cru_clksel_con[10],
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PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
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PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
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PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
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PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
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pclk_div << PERI_PCLK_DIV_SHIFT |
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hclk_div << PERI_HCLK_DIV_SHIFT |
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aclk_div << PERI_ACLK_DIV_SHIFT);
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/* PLL enter normal-mode */
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rk_clrsetreg(&cru->cru_mode_con,
|
|
GPLL_MODE_MASK << GPLL_MODE_SHIFT |
|
|
CPLL_MODE_MASK << CPLL_MODE_SHIFT,
|
|
GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
|
|
CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
|
|
|
|
rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000);
|
|
}
|
|
#endif
|
|
|
|
static ulong rk3188_clk_get_rate(struct clk *clk)
|
|
{
|
|
struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
|
|
ulong new_rate, gclk_rate;
|
|
|
|
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
|
|
switch (clk->id) {
|
|
case 1 ... 4:
|
|
new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
|
|
break;
|
|
case HCLK_EMMC:
|
|
case HCLK_SDMMC:
|
|
case HCLK_SDIO:
|
|
case SCLK_EMMC:
|
|
case SCLK_SDMMC:
|
|
case SCLK_SDIO:
|
|
new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
|
|
clk->id);
|
|
break;
|
|
case SCLK_SPI0:
|
|
case SCLK_SPI1:
|
|
new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ,
|
|
clk->id);
|
|
break;
|
|
case PCLK_I2C0:
|
|
case PCLK_I2C1:
|
|
case PCLK_I2C2:
|
|
case PCLK_I2C3:
|
|
case PCLK_I2C4:
|
|
return gclk_rate;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
return new_rate;
|
|
}
|
|
|
|
static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
|
|
struct rk3188_cru *cru = priv->cru;
|
|
ulong new_rate;
|
|
|
|
switch (clk->id) {
|
|
case PLL_APLL:
|
|
new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate,
|
|
priv->has_bwadj);
|
|
break;
|
|
case CLK_DDR:
|
|
new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate,
|
|
priv->has_bwadj);
|
|
break;
|
|
case HCLK_EMMC:
|
|
case HCLK_SDMMC:
|
|
case HCLK_SDIO:
|
|
case SCLK_EMMC:
|
|
case SCLK_SDMMC:
|
|
case SCLK_SDIO:
|
|
new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
|
|
clk->id, rate);
|
|
break;
|
|
case SCLK_SPI0:
|
|
case SCLK_SPI1:
|
|
new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ,
|
|
clk->id, rate);
|
|
break;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
return new_rate;
|
|
}
|
|
|
|
static struct clk_ops rk3188_clk_ops = {
|
|
.get_rate = rk3188_clk_get_rate,
|
|
.set_rate = rk3188_clk_set_rate,
|
|
};
|
|
|
|
static int rk3188_clk_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
struct rk3188_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->cru = dev_read_addr_ptr(dev);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk3188_clk_probe(struct udevice *dev)
|
|
{
|
|
struct rk3188_clk_priv *priv = dev_get_priv(dev);
|
|
enum rk3188_clk_type type = dev_get_driver_data(dev);
|
|
|
|
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
|
if (IS_ERR(priv->grf))
|
|
return PTR_ERR(priv->grf);
|
|
priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0;
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
struct rk3188_clk_plat *plat = dev_get_platdata(dev);
|
|
|
|
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
|
|
#endif
|
|
|
|
rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
|
|
|
|
/* Init CPU frequency */
|
|
rkclk_configure_cpu(priv->cru, priv->grf, APLL_HZ, priv->has_bwadj);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk3188_clk_bind(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
struct udevice *sys_child;
|
|
struct sysreset_reg *priv;
|
|
|
|
/* The reset driver does not have a device node, so bind it here */
|
|
ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
|
|
&sys_child);
|
|
if (ret) {
|
|
debug("Warning: No sysreset driver: ret=%d\n", ret);
|
|
} else {
|
|
priv = malloc(sizeof(struct sysreset_reg));
|
|
priv->glb_srst_fst_value = offsetof(struct rk3188_cru,
|
|
cru_glb_srst_fst_value);
|
|
priv->glb_srst_snd_value = offsetof(struct rk3188_cru,
|
|
cru_glb_srst_snd_value);
|
|
sys_child->priv = priv;
|
|
}
|
|
|
|
#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
|
|
ret = offsetof(struct rk3188_cru, cru_softrst_con[0]);
|
|
ret = rockchip_reset_bind(dev, ret, 9);
|
|
if (ret)
|
|
debug("Warning: software reset driver bind faile\n");
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id rk3188_clk_ids[] = {
|
|
{ .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU },
|
|
{ .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(rockchip_rk3188_cru) = {
|
|
.name = "rockchip_rk3188_cru",
|
|
.id = UCLASS_CLK,
|
|
.of_match = rk3188_clk_ids,
|
|
.priv_auto_alloc_size = sizeof(struct rk3188_clk_priv),
|
|
.platdata_auto_alloc_size = sizeof(struct rk3188_clk_plat),
|
|
.ops = &rk3188_clk_ops,
|
|
.bind = rk3188_clk_bind,
|
|
.ofdata_to_platdata = rk3188_clk_ofdata_to_platdata,
|
|
.probe = rk3188_clk_probe,
|
|
};
|