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![York Sun](/assets/img/avatar_default.png)
Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
323 lines
8.5 KiB
C
323 lines
8.5 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* calculate the organization and timing parameter
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* from ddr3 spd, please refer to the spec
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* JEDEC standard No.21-C 4_01_02_12R23A.pdf
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*
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*
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr.h>
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/*
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* Calculate the Density of each Physical Rank.
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* Returned size is in bytes.
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*
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* Total DIMM size =
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* sdram capacity(bit) / 8 * primary bus width / sdram width
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* * Logical Ranks per DIMM
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*
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* where: sdram capacity = spd byte4[3:0]
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* primary bus width = spd byte13[2:0]
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* sdram width = spd byte12[2:0]
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* Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP
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* spd byte12{5:3] * spd byte6[6:4] for 3DS
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*
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* To simplify each rank size = total DIMM size / Number of Package Ranks
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* where Number of Package Ranks = spd byte12[5:3]
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*
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* SPD byte4 - sdram density and banks
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* bit[3:0] size(bit) size(byte)
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* 0000 256Mb 32MB
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* 0001 512Mb 64MB
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* 0010 1Gb 128MB
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* 0011 2Gb 256MB
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* 0100 4Gb 512MB
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* 0101 8Gb 1GB
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* 0110 16Gb 2GB
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* 0111 32Gb 4GB
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*
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* SPD byte13 - module memory bus width
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* bit[2:0] primary bus width
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* 000 8bits
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* 001 16bits
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* 010 32bits
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* 011 64bits
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*
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* SPD byte12 - module organization
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* bit[2:0] sdram device width
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* 000 4bits
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* 001 8bits
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* 010 16bits
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* 011 32bits
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*
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* SPD byte12 - module organization
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* bit[5:3] number of package ranks per DIMM
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* 000 1
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* 001 2
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* 010 3
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* 011 4
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*
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* SPD byte6 - SDRAM package type
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* bit[6:4] Die count
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* 000 1
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* 001 2
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* 010 3
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* 011 4
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* 100 5
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* 101 6
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* 110 7
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* 111 8
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*
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* SPD byte6 - SRAM package type
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* bit[1:0] Signal loading
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* 00 Not specified
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* 01 Multi load stack
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* 10 Sigle load stack (3DS)
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* 11 Reserved
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*/
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static unsigned long long
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compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
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{
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unsigned long long bsize;
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int nbit_sdram_cap_bsize = 0;
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int nbit_primary_bus_width = 0;
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int nbit_sdram_width = 0;
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int die_count = 0;
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bool package_3ds;
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if ((spd->density_banks & 0xf) <= 7)
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nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
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if ((spd->bus_width & 0x7) < 4)
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nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
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if ((spd->organization & 0x7) < 4)
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nbit_sdram_width = (spd->organization & 0x7) + 2;
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package_3ds = (spd->package_type & 0x3) == 0x2;
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if (package_3ds)
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die_count = (spd->package_type >> 4) & 0x7;
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bsize = 1ULL << (nbit_sdram_cap_bsize - 3 +
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nbit_primary_bus_width - nbit_sdram_width +
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die_count);
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debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
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return bsize;
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}
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#define spd_to_ps(mtb, ftb) \
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(mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10)
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/*
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* ddr_compute_dimm_parameters for DDR4 SPD
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*
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* Compute DIMM parameters based upon the SPD information in spd.
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* Writes the results to the dimm_params_t structure pointed by pdimm.
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*
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*/
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unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
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const generic_spd_eeprom_t *spd,
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dimm_params_t *pdimm,
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unsigned int dimm_number)
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{
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unsigned int retval;
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int i;
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const u8 udimm_rc_e_dq[18] = {
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0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15,
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0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36
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};
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int spd_error = 0;
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u8 *ptr;
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if (spd->mem_type) {
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if (spd->mem_type != SPD_MEMTYPE_DDR4) {
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printf("DIMM %u: is not a DDR4 SPD.\n", dimm_number);
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return 1;
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}
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} else {
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memset(pdimm, 0, sizeof(dimm_params_t));
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return 1;
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}
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retval = ddr4_spd_check(spd);
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if (retval) {
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printf("DIMM %u: failed checksum\n", dimm_number);
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return 2;
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}
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/*
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* The part name in ASCII in the SPD EEPROM is not null terminated.
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* Guarantee null termination here by presetting all bytes to 0
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* and copying the part name in ASCII from the SPD onto it
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*/
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memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
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if ((spd->info_size_crc & 0xF) > 2)
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memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
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/* DIMM organization parameters */
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pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
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pdimm->rank_density = compute_ranksize(spd);
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pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
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pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
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if ((spd->bus_width >> 3) & 0x3)
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pdimm->ec_sdram_width = 8;
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else
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pdimm->ec_sdram_width = 0;
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pdimm->data_width = pdimm->primary_sdram_width
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+ pdimm->ec_sdram_width;
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pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
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/* These are the types defined by the JEDEC SPD spec */
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pdimm->mirrored_dimm = 0;
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pdimm->registered_dimm = 0;
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switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) {
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case DDR4_SPD_MODULETYPE_RDIMM:
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/* Registered/buffered DIMMs */
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pdimm->registered_dimm = 1;
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break;
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case DDR4_SPD_MODULETYPE_UDIMM:
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case DDR4_SPD_MODULETYPE_SO_DIMM:
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/* Unbuffered DIMMs */
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if (spd->mod_section.unbuffered.addr_mapping & 0x1)
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pdimm->mirrored_dimm = 1;
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if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 &&
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(spd->mod_section.unbuffered.ref_raw_card == 0x04)) {
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/* Fix SPD error found on DIMMs with raw card E0 */
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for (i = 0; i < 18; i++) {
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if (spd->mapping[i] == udimm_rc_e_dq[i])
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continue;
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spd_error = 1;
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debug("SPD byte %d: 0x%x, should be 0x%x\n",
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60 + i, spd->mapping[i],
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udimm_rc_e_dq[i]);
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ptr = (u8 *)&spd->mapping[i];
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*ptr = udimm_rc_e_dq[i];
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}
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if (spd_error)
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puts("SPD DQ mapping error fixed\n");
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}
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break;
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default:
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printf("unknown module_type 0x%02X\n", spd->module_type);
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return 1;
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}
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/* SDRAM device parameters */
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pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
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pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
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pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
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pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
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/*
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* The SPD spec has not the ECC bit,
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* We consider the DIMM as ECC capability
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* when the extension bus exist
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*/
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if (pdimm->ec_sdram_width)
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pdimm->edc_config = 0x02;
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else
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pdimm->edc_config = 0x00;
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/*
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* The SPD spec has not the burst length byte
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* but DDR4 spec has nature BL8 and BC4,
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* BL8 -bit3, BC4 -bit2
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*/
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pdimm->burst_lengths_bitmask = 0x0c;
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pdimm->row_density = __ilog2(pdimm->rank_density);
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/* MTB - medium timebase
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* The MTB in the SPD spec is 125ps,
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*
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* FTB - fine timebase
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* use 1/10th of ps as our unit to avoid floating point
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* eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
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*/
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if ((spd->timebases & 0xf) == 0x0) {
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pdimm->mtb_ps = 125;
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pdimm->ftb_10th_ps = 10;
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} else {
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printf("Unknown Timebases\n");
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}
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/* sdram minimum cycle time */
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pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
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/* sdram max cycle time */
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pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
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/*
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* CAS latency supported
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* bit0 - CL7
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* bit4 - CL11
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* bit8 - CL15
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* bit12- CL19
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* bit16- CL23
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*/
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pdimm->caslat_x = (spd->caslat_b1 << 7) |
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(spd->caslat_b2 << 15) |
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(spd->caslat_b3 << 23);
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BUG_ON(spd->caslat_b4 != 0);
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/*
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* min CAS latency time
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*/
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pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
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/*
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* min RAS to CAS delay time
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*/
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pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
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/*
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* Min Row Precharge Delay Time
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*/
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pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
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/* min active to precharge delay time */
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pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
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spd->tras_min_lsb) * pdimm->mtb_ps;
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/* min active to actice/refresh delay time */
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pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
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spd->trc_min_lsb), spd->fine_trc_min);
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/* Min Refresh Recovery Delay Time */
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pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
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pdimm->mtb_ps;
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pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
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pdimm->mtb_ps;
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pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
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pdimm->mtb_ps;
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/* min four active window delay time */
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pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
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pdimm->mtb_ps;
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/* min row active to row active delay time, different bank group */
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pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
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/* min row active to row active delay time, same bank group */
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pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
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/* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */
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pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
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/*
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* Average periodic refresh interval
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* tREFI = 7.8 us at normal temperature range
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*/
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pdimm->refresh_rate_ps = 7800000;
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for (i = 0; i < 18; i++)
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pdimm->dq_mapping[i] = spd->mapping[i];
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pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;
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return 0;
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}
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