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https://github.com/brain-hackers/u-boot-brain
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c4775476d2
Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux.
However it has a weird DMA alignment issue:
(1) Tx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: O.K
(2) Rx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: Invalid!!!
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Tom Rini <trini@ti.com>
178 lines
6.9 KiB
C
178 lines
6.9 KiB
C
/*
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* Faraday 10/100Mbps Ethernet Controller
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*
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* (C) Copyright 2010 Faraday Technology
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* Dante Su <dantesu@faraday-tech.com>
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*
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* This file is released under the terms of GPL v2 and any later version.
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* See the file COPYING in the root directory of the source tree for details.
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*/
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#ifndef _FTMAC110_H
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#define _FTMAC110_H
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struct ftmac110_regs {
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uint32_t isr; /* 0x00: Interrups Status Register */
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uint32_t imr; /* 0x04: Interrupt Mask Register */
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uint32_t mac[2]; /* 0x08: MAC Address */
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uint32_t mht[2]; /* 0x10: Multicast Hash Table Register */
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uint32_t txpd; /* 0x18: Tx Poll Demand Register */
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uint32_t rxpd; /* 0x1c: Rx Poll Demand Register */
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uint32_t txba; /* 0x20: Tx Ring Base Address Register */
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uint32_t rxba; /* 0x24: Rx Ring Base Address Register */
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uint32_t itc; /* 0x28: Interrupt Timer Control Register */
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uint32_t aptc; /* 0x2C: Automatic Polling Timer Control Register */
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uint32_t dblac; /* 0x30: DMA Burst Length&Arbitration Control */
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uint32_t revr; /* 0x34: Revision Register */
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uint32_t fear; /* 0x38: Feature Register */
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uint32_t rsvd[19];
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uint32_t maccr; /* 0x88: MAC Control Register */
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uint32_t macsr; /* 0x8C: MAC Status Register */
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uint32_t phycr; /* 0x90: PHY Control Register */
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uint32_t phydr; /* 0x94: PHY Data Register */
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uint32_t fcr; /* 0x98: Flow Control Register */
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uint32_t bpr; /* 0x9C: Back Pressure Register */
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};
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/*
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* Interrupt status/mask register(ISR/IMR) bits
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*/
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#define ISR_ALL 0x3ff
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#define ISR_PHYSTCHG (1 << 9) /* phy status change */
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#define ISR_AHBERR (1 << 8) /* bus error */
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#define ISR_RXLOST (1 << 7) /* rx lost */
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#define ISR_RXFIFO (1 << 6) /* rx to fifo */
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#define ISR_TXLOST (1 << 5) /* tx lost */
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#define ISR_TXOK (1 << 4) /* tx to ethernet */
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#define ISR_NOTXBUF (1 << 3) /* out of tx buffer */
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#define ISR_TXFIFO (1 << 2) /* tx to fifo */
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#define ISR_NORXBUF (1 << 1) /* out of rx buffer */
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#define ISR_RXOK (1 << 0) /* rx to buffer */
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/*
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* MACCR control bits
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*/
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#define MACCR_100M (1 << 18) /* 100Mbps mode */
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#define MACCR_RXBCST (1 << 17) /* rx broadcast packet */
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#define MACCR_RXMCST (1 << 16) /* rx multicast packet */
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#define MACCR_FD (1 << 15) /* full duplex */
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#define MACCR_CRCAPD (1 << 14) /* tx crc append */
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#define MACCR_RXALL (1 << 12) /* rx all packets */
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#define MACCR_RXFTL (1 << 11) /* rx packet even it's > 1518 byte */
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#define MACCR_RXRUNT (1 << 10) /* rx packet even it's < 64 byte */
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#define MACCR_RXMCSTHT (1 << 9) /* rx multicast hash table */
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#define MACCR_RXEN (1 << 8) /* rx enable */
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#define MACCR_RXINHDTX (1 << 6) /* rx in half duplex tx */
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#define MACCR_TXEN (1 << 5) /* tx enable */
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#define MACCR_CRCDIS (1 << 4) /* tx packet even it's crc error */
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#define MACCR_LOOPBACK (1 << 3) /* loop-back */
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#define MACCR_RESET (1 << 2) /* reset */
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#define MACCR_RXDMAEN (1 << 1) /* rx dma enable */
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#define MACCR_TXDMAEN (1 << 0) /* tx dma enable */
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/*
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* PHYCR control bits
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*/
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#define PHYCR_READ (1 << 26)
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#define PHYCR_WRITE (1 << 27)
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#define PHYCR_REG_SHIFT 21
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#define PHYCR_ADDR_SHIFT 16
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/*
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* ITC control bits
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*/
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/* Tx Cycle Length */
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#define ITC_TX_CYCLONG (1 << 15) /* 100Mbps=81.92us; 10Mbps=819.2us */
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#define ITC_TX_CYCNORM (0 << 15) /* 100Mbps=5.12us; 10Mbps=51.2us */
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/* Tx Threshold: Aggregate n interrupts as 1 interrupt */
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#define ITC_TX_THR(n) (((n) & 0x7) << 12)
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/* Tx Interrupt Timeout = n * Tx Cycle */
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#define ITC_TX_ITMO(n) (((n) & 0xf) << 8)
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/* Rx Cycle Length */
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#define ITC_RX_CYCLONG (1 << 7) /* 100Mbps=81.92us; 10Mbps=819.2us */
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#define ITC_RX_CYCNORM (0 << 7) /* 100Mbps=5.12us; 10Mbps=51.2us */
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/* Rx Threshold: Aggregate n interrupts as 1 interrupt */
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#define ITC_RX_THR(n) (((n) & 0x7) << 4)
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/* Rx Interrupt Timeout = n * Rx Cycle */
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#define ITC_RX_ITMO(n) (((n) & 0xf) << 0)
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#define ITC_DEFAULT \
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(ITC_TX_THR(1) | ITC_TX_ITMO(0) | ITC_RX_THR(1) | ITC_RX_ITMO(0))
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/*
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* APTC contrl bits
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*/
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/* Tx Cycle Length */
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#define APTC_TX_CYCLONG (1 << 12) /* 100Mbps=81.92us; 10Mbps=819.2us */
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#define APTC_TX_CYCNORM (0 << 12) /* 100Mbps=5.12us; 10Mbps=51.2us */
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/* Tx Poll Timeout = n * Tx Cycle, 0=No auto polling */
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#define APTC_TX_PTMO(n) (((n) & 0xf) << 8)
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/* Rx Cycle Length */
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#define APTC_RX_CYCLONG (1 << 4) /* 100Mbps=81.92us; 10Mbps=819.2us */
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#define APTC_RX_CYCNORM (0 << 4) /* 100Mbps=5.12us; 10Mbps=51.2us */
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/* Rx Poll Timeout = n * Rx Cycle, 0=No auto polling */
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#define APTC_RX_PTMO(n) (((n) & 0xf) << 0)
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#define APTC_DEFAULT (APTC_TX_PTMO(0) | APTC_RX_PTMO(1))
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/*
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* DBLAC contrl bits
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*/
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#define DBLAC_BURST_MAX_ANY (0 << 14) /* un-limited */
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#define DBLAC_BURST_MAX_32X4 (2 << 14) /* max = 32 x 4 bytes */
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#define DBLAC_BURST_MAX_64X4 (3 << 14) /* max = 64 x 4 bytes */
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#define DBLAC_RXTHR_EN (1 << 9) /* enable rx threshold arbitration */
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#define DBLAC_RXTHR_HIGH(n) (((n) & 0x7) << 6) /* upper bound = n/8 fifo */
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#define DBLAC_RXTHR_LOW(n) (((n) & 0x7) << 3) /* lower bound = n/8 fifo */
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#define DBLAC_BURST_CAP16 (1 << 2) /* support burst 16 */
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#define DBLAC_BURST_CAP8 (1 << 1) /* support burst 8 */
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#define DBLAC_BURST_CAP4 (1 << 0) /* support burst 4 */
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#define DBLAC_DEFAULT \
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(DBLAC_RXTHR_EN | DBLAC_RXTHR_HIGH(6) | DBLAC_RXTHR_LOW(2))
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/*
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* descriptor structure
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*/
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struct ftmac110_rxd {
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uint32_t ct[2];
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uint32_t buf;
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void *vbuf; /* reserved */
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};
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#define FTMAC110_RXCT0_OWNER BIT_MASK(31) /* owner: 1=HW, 0=SW */
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#define FTMAC110_RXCT0_FRS BIT_MASK(29) /* first pkt desc */
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#define FTMAC110_RXCT0_LRS BIT_MASK(28) /* last pkt desc */
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#define FTMAC110_RXCT0_ODDNB BIT_MASK(22) /* odd nibble */
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#define FTMAC110_RXCT0_RUNT BIT_MASK(21) /* runt pkt */
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#define FTMAC110_RXCT0_FTL BIT_MASK(20) /* frame too long */
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#define FTMAC110_RXCT0_CRC BIT_MASK(19) /* pkt crc error */
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#define FTMAC110_RXCT0_ERR BIT_MASK(18) /* bus error */
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#define FTMAC110_RXCT0_ERRMASK (0x1f << 18) /* all errors */
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#define FTMAC110_RXCT0_BCST BIT_MASK(17) /* Bcst pkt */
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#define FTMAC110_RXCT0_MCST BIT_MASK(16) /* Mcst pkt */
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#define FTMAC110_RXCT0_LEN(x) ((x) & 0x7ff)
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#define FTMAC110_RXCT1_END BIT_MASK(31)
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#define FTMAC110_RXCT1_BUFSZ(x) ((x) & 0x7ff)
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struct ftmac110_txd {
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uint32_t ct[2];
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uint32_t buf;
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void *vbuf; /* reserved */
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};
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#define FTMAC110_TXCT0_OWNER BIT_MASK(31) /* owner: 1=HW, 0=SW */
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#define FTMAC110_TXCT0_COL 0x00000003 /* collision */
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#define FTMAC110_TXCT1_END BIT_MASK(31) /* end of ring */
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#define FTMAC110_TXCT1_TXIC BIT_MASK(30) /* tx done interrupt */
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#define FTMAC110_TXCT1_TX2FIC BIT_MASK(29) /* tx fifo interrupt */
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#define FTMAC110_TXCT1_FTS BIT_MASK(28) /* first pkt desc */
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#define FTMAC110_TXCT1_LTS BIT_MASK(27) /* last pkt desc */
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#define FTMAC110_TXCT1_LEN(x) ((x) & 0x7ff)
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#endif /* FTMAC110_H */
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