mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-10 06:43:28 +09:00
![wdenk](/assets/img/avatar_default.png)
- DDR Ram support for PM520 (MPC5200) - support for different flash types (PM520) - USB / IDE / CF-Card / DiskOnChip support for PM520 - 8 bit boot rom support for PM520/CE520 - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245) - I2C and RTC support for CPC45 - support of new flash type (28F160C3T) for CPC45
134 lines
3.3 KiB
C
134 lines
3.3 KiB
C
/*
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* cpu/mc9328/serial.c
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*
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* (c) Copyright 2004
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* Techware Information Technology, Inc.
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* http://www.techware.com.tw/
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*
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* Ming-Len Wu <minglen_wu@techware.com.tw>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mc9328.h>
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#if defined(CONFIG_UART1)
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/* GPIO PORT B */
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#define reg_GIUS MX1_GIUS_C
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#define reg_GPR MX1_GPR_B
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#define GPIO_MASK 0xFFFFE1FF
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#define UART_BASE 0x00206000
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#elif defined (CONFIG_UART2)
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/* GPIO PORT C */
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#define reg_GIUS MX1_GIUS_C
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#define reg_GPR MX1_GPR_C
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#define GPIO_MASK 0x0FFFFFFF
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#define UART_BASE 0x207000
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#endif
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#define reg_URXD (*((volatile u32 *)(UART_BASE+0x00)))
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#define reg_UTXD (*((volatile u32 *)(UART_BASE+0x40)))
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#define reg_UCR1 (*((volatile u32 *)(UART_BASE+0x80)))
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#define reg_UCR2 (*((volatile u32 *)(UART_BASE+0x84)))
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#define reg_UCR3 (*((volatile u32 *)(UART_BASE+0x88)))
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#define reg_UCR4 (*((volatile u32 *)(UART_BASE+0x8C)))
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#define reg_UFCR (*((volatile u32 *)(UART_BASE+0x90)))
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#define reg_USR1 (*((volatile u32 *)(UART_BASE+0x94)))
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#define reg_USR2 (*((volatile u32 *)(UART_BASE+0x98)))
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#define reg_UESC (*((volatile u32 *)(UART_BASE+0x9C)))
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#define reg_UTIM (*((volatile u32 *)(UART_BASE+0xA0)))
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#define reg_UBIR (*((volatile u32 *)(UART_BASE+0xA4)))
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#define reg_UBMR (*((volatile u32 *)(UART_BASE+0xA8)))
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#define reg_UBRC (*((volatile u32 *)(UART_BASE+0xAC)))
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#define TXFE_MASK 0x4000 /* Tx buffer empty */
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#define RDR_MASK 0x0001 /* receive data ready */
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void serial_setbrg (void) {
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/* config I/O pins for UART */
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reg_GIUS &= GPIO_MASK;
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reg_GPR &= GPIO_MASK;
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/* config UART */
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reg_UCR1 = 5;
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reg_UCR2 = 0x4027;
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reg_UCR4 = 1;
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reg_UFCR = 0xA81;
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reg_UBIR = 0xF;
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reg_UBMR = 0x8A;
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reg_UBRC = 8;
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}
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/*
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*
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*/
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int serial_init (void) {
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serial_setbrg ();
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return (0);
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}
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/*
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* Read a single byte from the serial port. Returns 1 on success, 0
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* otherwise. When the function is succesfull, the character read is
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* written into its argument c.
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*/
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int serial_getc (void) {
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while (!(reg_USR2 & RDR_MASK)) ; /* wait until RDR bit set */
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return (u8)reg_URXD;
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}
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/*
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* Output a single byte to the serial port.
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*/
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void serial_putc (const char c) {
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while (!(reg_USR2 & TXFE_MASK)); /* wait until TXFE bit set */
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reg_UTXD = (u16) c;
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if (c == '\n') { /* carriage return ? append line-feed */
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while (!(reg_USR2 & TXFE_MASK)); /* wait until TXFE bit set */
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reg_UTXD = '\r';
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}
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}
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/*
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* Test whether a character is in the RX buffer
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*/
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int serial_tstc (void) {
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return reg_USR2 & RDR_MASK;
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}
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void serial_puts (const char *s) {
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while (*s) {
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serial_putc (*s++);
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}
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}
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