mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-08 04:06:15 +09:00
468ba8d00b
Add initial support for the ABB SECU board, which is an ArriaV-based SoCFPGA system with ethernet and booting from Denali NAND. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
328 lines
8.7 KiB
C
328 lines
8.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Altera SoCFPGA SDRAM configuration
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*
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*/
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#ifndef __SOCFPGA_SDRAM_CONFIG_H__
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#define __SOCFPGA_SDRAM_CONFIG_H__
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/* SDRAM configuration */
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#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
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#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
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#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
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#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
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#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
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#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
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#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
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#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
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#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
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#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
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#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
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#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
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#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
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#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
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#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
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#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
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#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
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#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
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#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
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#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
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/* Sequencer auto configuration */
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#define RW_MGR_ACTIVATE_0_AND_1 0x11
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#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x12
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#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x14
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#define RW_MGR_CLEAR_DQS_ENABLE 0x4B
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#define RW_MGR_EMR 0x09
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#define RW_MGR_EMR2 0x0D
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#define RW_MGR_EMR3 0x0F
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#define RW_MGR_EMR_OCD_ENABLE 0x0B
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#define RW_MGR_GUARANTEED_READ 0x4E
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#define RW_MGR_GUARANTEED_READ_CONT 0x56
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#define RW_MGR_GUARANTEED_WRITE 0x1A
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#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1D
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#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x21
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#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x1B
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#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1F
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#define RW_MGR_IDLE 0x00
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#define RW_MGR_IDLE_LOOP1 0x77
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#define RW_MGR_IDLE_LOOP2 0x76
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#define RW_MGR_INIT_CKE_0 0x71
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#define RW_MGR_LFSR_WR_RD_BANK_0 0x24
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#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x27
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#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x26
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#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x25
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#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x34
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#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x23
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x38
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x3B
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x3A
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x39
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x48
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x37
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#define RW_MGR_MR_CALIB 0x05
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#define RW_MGR_MR_DLL_RESET 0x07
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#define RW_MGR_MR_USER 0x03
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#define RW_MGR_NOP 0x01
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#define RW_MGR_PRECHARGE_ALL 0x16
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#define RW_MGR_READ_B2B 0x5B
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#define RW_MGR_READ_B2B_WAIT1 0x63
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#define RW_MGR_READ_B2B_WAIT2 0x6D
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#define RW_MGR_REFRESH 0x18
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/* Sequencer defines configuration */
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#define AFI_CLK_FREQ 301
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#define AFI_RATE_RATIO 1
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#define CALIB_LFIFO_OFFSET 6
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#define CALIB_VFIFO_OFFSET 4
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#define ENABLE_SUPER_QUICK_CALIBRATION 0
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#define IO_DELAY_PER_DCHAIN_TAP 25
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#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
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#define IO_DELAY_PER_OPA_TAP 416
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#define IO_DLL_CHAIN_LENGTH 8
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#define IO_DQDQS_OUT_PHASE_MAX 0
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#define IO_DQS_EN_DELAY_MAX 31
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#define IO_DQS_EN_DELAY_OFFSET 0
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#define IO_DQS_EN_PHASE_MAX 7
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#define IO_DQS_IN_DELAY_MAX 31
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#define IO_DQS_IN_RESERVE 4
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#define IO_DQS_OUT_RESERVE 4
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#define IO_IO_IN_DELAY_MAX 31
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#define IO_IO_OUT1_DELAY_MAX 31
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#define IO_IO_OUT2_DELAY_MAX 0
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#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
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#define MAX_LATENCY_COUNT_WIDTH 5
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#define READ_VALID_FIFO_SIZE 16
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#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504bf
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#define RW_MGR_MEM_ADDRESS_MIRRORING 0
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#define RW_MGR_MEM_DATA_MASK_WIDTH 4
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#define RW_MGR_MEM_DATA_WIDTH 32
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#define RW_MGR_MEM_DQ_PER_READ_DQS 8
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#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
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#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
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#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
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#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
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#define RW_MGR_MEM_NUMBER_OF_RANKS 1
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#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
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#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
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#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
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#define TINIT_CNTR0_VAL 74
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#define TINIT_CNTR1_VAL 20
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#define TINIT_CNTR2_VAL 20
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#define TRESET_CNTR0_VAL 74
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#define TRESET_CNTR1_VAL 99
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#define TRESET_CNTR2_VAL 10
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/* Sequencer ac_rom_init configuration */
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const u32 ac_rom_init[] = {
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0x30700000,
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0x38700000,
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0x30700000,
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0x20700000,
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0x10000853,
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0x10000853,
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0x10000953,
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0x10010000,
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0x10010380,
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0x10020000,
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0x10030000,
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0x10300400,
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0x10600000,
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0x10620000,
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0x10200400,
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0x10400000,
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0x1c900000,
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0x1c920000,
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0x1c900008,
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0x1c920008,
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0x38f00000,
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0x3cf00000,
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0x38700000,
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0x10100000,
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0x18900000,
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0x13500000,
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0x13520000,
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0x13500008,
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0x13520008,
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0x33700000,
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0x10500008
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};
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/* Sequencer inst_rom_init configuration */
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const u32 inst_rom_init[] = {
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0x80180,
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0x100,
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0x80000,
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0x200,
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0x80000,
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0x280,
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0x80000,
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0x300,
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0x80000,
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0x380,
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0x80000,
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0x400,
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0x80000,
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0x480,
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0x80000,
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0x500,
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0x80000,
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0x600,
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0x8000,
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0x680,
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0xa000,
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0x80000,
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0x700,
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0x80000,
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0x780,
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0x80000,
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0x968,
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0xcae8,
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0x8e8,
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0x8ae8,
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0x988,
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0xea88,
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0x808,
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0xaa88,
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0x80000,
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0xcc00,
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0xcb80,
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0xe080,
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0xa00,
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0x20ae0,
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0x20ae0,
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0x20ae0,
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0x20ae0,
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0xb00,
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0x0,
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0x0,
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0x0,
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0x0,
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0x60c80,
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0x60e80,
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0x60e80,
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0x60e80,
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0xa000,
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0x8000,
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0x80000,
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0xcc00,
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0xcb80,
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0xe080,
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0xa00,
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0x30ae0,
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0x30ae0,
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0x30ae0,
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0x30ae0,
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0xb00,
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0x0,
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0x0,
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0x0,
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0x0,
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0x70c80,
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0x70e80,
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0x70e80,
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0x70e80,
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0xa000,
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0x8000,
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0x80000,
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0xf58,
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0x58,
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0x80000,
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0xf68,
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0x168,
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0x168,
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0x8168,
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0x40de8,
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0x40ee8,
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0x40ee8,
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0x40ee8,
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0xf68,
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0x168,
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0x168,
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0xa168,
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0x80000,
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0x40c88,
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0x40e88,
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0x40e88,
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0x40e88,
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0x40d68,
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0x40ee8,
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0x40ee8,
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0x40ee8,
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0xa000,
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0x40de8,
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0x40ee8,
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0x40ee8,
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0x40ee8,
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0x40e08,
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0x40e88,
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0x40e88,
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0x40e88,
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0xf00,
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0xc000,
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0x8000,
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0xe000,
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0x80000,
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0x180,
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0x8180,
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0xa180,
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0xc180,
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0x80180,
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0x8000,
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0xa000,
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0x80000
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};
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#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
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