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![]() Activate cache on DDR to improve the accesses to DDR used by SPL: - CONFIG_SPL_BSS_START_ADDR - CONFIG_SYS_SPL_MALLOC_START Cache is configured only when DDR is fully initialized, to avoid speculative access and issue in get_ram_size(). Data cache is deactivated at the end of SPL, to flush the data cache and the TLB. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
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.. | ||
cmd_stm32prog | ||
include/mach | ||
boot_params.c | ||
bsec.c | ||
cmd_stm32key.c | ||
config.mk | ||
cpu.c | ||
dram_init.c | ||
fdt.c | ||
Kconfig | ||
Makefile | ||
psci.c | ||
pwr_regulator.c | ||
spl.c | ||
syscon.c |