mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 21:33:24 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
62 lines
1.3 KiB
C
62 lines
1.3 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
|
|
/*
|
|
* Clock drivers for Qualcomm APQ8096
|
|
*
|
|
* (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
|
|
*
|
|
* Based on Little Kernel driver, simplified
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <clk-uclass.h>
|
|
#include <dm.h>
|
|
#include <errno.h>
|
|
#include <asm/io.h>
|
|
#include <linux/bitops.h>
|
|
#include "clock-snapdragon.h"
|
|
|
|
/* GPLL0 clock control registers */
|
|
#define GPLL0_STATUS_ACTIVE BIT(30)
|
|
#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
|
|
|
|
static const struct bcr_regs sdc_regs = {
|
|
.cfg_rcgr = SDCC2_CFG_RCGR,
|
|
.cmd_rcgr = SDCC2_CMD_RCGR,
|
|
.M = SDCC2_M,
|
|
.N = SDCC2_N,
|
|
.D = SDCC2_D,
|
|
};
|
|
|
|
static const struct gpll0_ctrl gpll0_ctrl = {
|
|
.status = GPLL0_STATUS,
|
|
.status_bit = GPLL0_STATUS_ACTIVE,
|
|
.ena_vote = APCS_GPLL_ENA_VOTE,
|
|
.vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
|
|
};
|
|
|
|
static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
|
|
{
|
|
int div = 3;
|
|
|
|
clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
|
|
clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
|
|
CFG_CLK_SRC_GPLL0);
|
|
clk_enable_gpll0(priv->base, &gpll0_ctrl);
|
|
clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
|
|
|
|
return rate;
|
|
}
|
|
|
|
ulong msm_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
|
|
|
|
switch (clk->id) {
|
|
case 0: /* SDC1 */
|
|
return clk_init_sdc(priv, rate);
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|