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https://github.com/brain-hackers/u-boot-brain
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c41e660b6b
Enable FPGA reconfiguration support for Stratix 10 SoC. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
25 lines
834 B
Makefile
25 lines
834 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y += fpga.o
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obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
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obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
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obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
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obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
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obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
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obj-$(CONFIG_FPGA_XILINX) += xilinx.o
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obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
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ifdef CONFIG_FPGA_ALTERA
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obj-y += altera.o
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obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
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obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
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obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
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obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
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obj-$(CONFIG_FPGA_STRATIX10) += stratix10.o
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obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
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obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
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obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
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endif
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