mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-11 15:23:22 +09:00
![Stephen Warren](/assets/img/avatar_default.png)
This prevents the following boot-time message on any board where only the first DC is in use, yet the DC's DT node is enabled: stdio_add_devices: Video device failed (ret=-22) (This happens on at least Harmony, Ventana, and likely any other Tegra20 board with display enabled other than Seaboard). The Tegra DC's DT node represents a display controller. It may itself drive an integrated RGB display output, or be used by some other display controller such as HDMI. For this reason the DC node itself is not enabled/disabled in DT; the DC itself is considered a shared resource, not the final (board-specific) display output. The node should instantiate a display output driver only if the rgb subnode is enabled. Other output drivers are free to use the DC if they are enabled and their DT node references the DC's DT node. Adapt the Tegra display drivers' bind() routine to only bind to the DC's DT node if the RGB subnode is enabled. Now that the display driver does the right thing, remove the workaround for this issue from Seaboard's DT file. Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
655 lines
18 KiB
C
655 lines
18 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <pwm.h>
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#include <video.h>
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#include <asm/system.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/pwm.h>
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#include <asm/arch/display.h>
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#include <asm/arch-tegra/timer.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* These are the stages we go throuh in enabling the LCD */
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enum stage_t {
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STAGE_START,
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STAGE_PANEL_VDD,
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STAGE_LVDS,
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STAGE_BACKLIGHT_VDD,
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STAGE_PWM,
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STAGE_BACKLIGHT_EN,
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STAGE_DONE,
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};
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#define FDT_LCD_TIMINGS 4
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enum {
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FDT_LCD_TIMING_REF_TO_SYNC,
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FDT_LCD_TIMING_SYNC_WIDTH,
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FDT_LCD_TIMING_BACK_PORCH,
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FDT_LCD_TIMING_FRONT_PORCH,
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FDT_LCD_TIMING_COUNT,
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};
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enum lcd_cache_t {
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FDT_LCD_CACHE_OFF = 0,
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FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0,
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FDT_LCD_CACHE_WRITE_BACK = 1 << 1,
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FDT_LCD_CACHE_FLUSH = 1 << 2,
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FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK |
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FDT_LCD_CACHE_FLUSH,
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};
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/* Information about the display controller */
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struct tegra_lcd_priv {
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enum stage_t stage; /* Current stage we are at */
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unsigned long timer_next; /* Time we can move onto next stage */
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int width; /* width in pixels */
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int height; /* height in pixels */
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/*
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* log2 of number of bpp, in general, unless it bpp is 24 in which
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* case this field holds 24 also! This is a U-Boot thing.
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*/
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int log2_bpp;
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struct disp_ctlr *disp; /* Display controller to use */
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fdt_addr_t frame_buffer; /* Address of frame buffer */
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unsigned pixel_clock; /* Pixel clock in Hz */
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uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */
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uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */
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struct udevice *pwm;
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int pwm_channel; /* PWM channel to use for backlight */
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enum lcd_cache_t cache_type;
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struct gpio_desc backlight_en; /* GPIO for backlight enable */
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struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */
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struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */
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struct gpio_desc panel_vdd; /* GPIO for panel vdd */
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/*
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* Panel required timings
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* Timing 1: delay between panel_vdd-rise and data-rise
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* Timing 2: delay between data-rise and backlight_vdd-rise
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* Timing 3: delay between backlight_vdd and pwm-rise
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* Timing 4: delay between pwm-rise and backlight_en-rise
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*/
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uint panel_timings[FDT_LCD_TIMINGS];
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};
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enum {
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/* Maximum LCD size we support */
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LCD_MAX_WIDTH = 1366,
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LCD_MAX_HEIGHT = 768,
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LCD_MAX_LOG2_BPP = VIDEO_BPP16,
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};
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static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
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{
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unsigned h_dda, v_dda;
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unsigned long val;
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val = readl(&dc->cmd.disp_win_header);
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val |= WINDOW_A_SELECT;
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writel(val, &dc->cmd.disp_win_header);
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writel(win->fmt, &dc->win.color_depth);
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clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
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BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
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val = win->out_x << H_POSITION_SHIFT;
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val |= win->out_y << V_POSITION_SHIFT;
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writel(val, &dc->win.pos);
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val = win->out_w << H_SIZE_SHIFT;
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val |= win->out_h << V_SIZE_SHIFT;
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writel(val, &dc->win.size);
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val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
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val |= win->h << V_PRESCALED_SIZE_SHIFT;
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writel(val, &dc->win.prescaled_size);
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writel(0, &dc->win.h_initial_dda);
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writel(0, &dc->win.v_initial_dda);
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h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
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v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
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val = h_dda << H_DDA_INC_SHIFT;
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val |= v_dda << V_DDA_INC_SHIFT;
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writel(val, &dc->win.dda_increment);
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writel(win->stride, &dc->win.line_stride);
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writel(0, &dc->win.buf_stride);
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val = WIN_ENABLE;
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if (win->bpp < 24)
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val |= COLOR_EXPAND;
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writel(val, &dc->win.win_opt);
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writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
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writel(win->x, &dc->winbuf.addr_h_offset);
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writel(win->y, &dc->winbuf.addr_v_offset);
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writel(0xff00, &dc->win.blend_nokey);
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writel(0xff00, &dc->win.blend_1win);
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val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
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val |= GENERAL_UPDATE | WIN_A_UPDATE;
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writel(val, &dc->cmd.state_ctrl);
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}
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static void write_pair(struct tegra_lcd_priv *priv, int item, u32 *reg)
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{
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writel(priv->horiz_timing[item] |
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(priv->vert_timing[item] << 16), reg);
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}
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static int update_display_mode(struct dc_disp_reg *disp,
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struct tegra_lcd_priv *priv)
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{
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unsigned long val;
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unsigned long rate;
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unsigned long div;
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writel(0x0, &disp->disp_timing_opt);
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write_pair(priv, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
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write_pair(priv, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
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write_pair(priv, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
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write_pair(priv, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
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writel(priv->width | (priv->height << 16), &disp->disp_active);
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val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
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val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
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writel(val, &disp->data_enable_opt);
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val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
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val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
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val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
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writel(val, &disp->disp_interface_ctrl);
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/*
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* The pixel clock divider is in 7.1 format (where the bottom bit
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* represents 0.5). Here we calculate the divider needed to get from
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* the display clock (typically 600MHz) to the pixel clock. We round
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* up or down as requried.
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*/
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rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
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div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
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debug("Display clock %lu, divider %lu\n", rate, div);
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writel(0x00010001, &disp->shift_clk_opt);
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val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
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val |= div << SHIFT_CLK_DIVIDER_SHIFT;
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writel(val, &disp->disp_clk_ctrl);
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return 0;
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}
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/* Start up the display and turn on power to PWMs */
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static void basic_init(struct dc_cmd_reg *cmd)
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{
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u32 val;
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writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
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writel(0x0000011a, &cmd->cont_syncpt_vsync);
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writel(0x00000000, &cmd->int_type);
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writel(0x00000000, &cmd->int_polarity);
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writel(0x00000000, &cmd->int_mask);
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writel(0x00000000, &cmd->int_enb);
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val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
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val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
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val |= PM1_ENABLE;
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writel(val, &cmd->disp_pow_ctrl);
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val = readl(&cmd->disp_cmd);
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val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
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writel(val, &cmd->disp_cmd);
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}
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static void basic_init_timer(struct dc_disp_reg *disp)
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{
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writel(0x00000020, &disp->mem_high_pri);
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writel(0x00000001, &disp->mem_high_pri_timer);
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}
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static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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};
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static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
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0x00000000,
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0x01000000,
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0x00000000,
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0x00000000,
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};
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static const u32 rgb_data_tab[PIN_REG_COUNT] = {
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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};
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static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00210222,
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0x00002200,
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0x00020000,
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};
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static void rgb_enable(struct dc_com_reg *com)
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{
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int i;
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for (i = 0; i < PIN_REG_COUNT; i++) {
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writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
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writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
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writel(rgb_data_tab[i], &com->pin_output_data[i]);
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}
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for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
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writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
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}
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static int setup_window(struct disp_ctl_win *win,
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struct tegra_lcd_priv *priv)
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{
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win->x = 0;
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win->y = 0;
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win->w = priv->width;
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win->h = priv->height;
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win->out_x = 0;
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win->out_y = 0;
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win->out_w = priv->width;
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win->out_h = priv->height;
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win->phys_addr = priv->frame_buffer;
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win->stride = priv->width * (1 << priv->log2_bpp) / 8;
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debug("%s: depth = %d\n", __func__, priv->log2_bpp);
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switch (priv->log2_bpp) {
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case 5:
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case 24:
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win->fmt = COLOR_DEPTH_R8G8B8A8;
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win->bpp = 32;
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break;
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case 4:
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win->fmt = COLOR_DEPTH_B5G6R5;
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win->bpp = 16;
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break;
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default:
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debug("Unsupported LCD bit depth");
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return -1;
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}
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return 0;
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}
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static void debug_timing(const char *name, unsigned int timing[])
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{
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#ifdef DEBUG
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int i;
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debug("%s timing: ", name);
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for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
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debug("%d ", timing[i]);
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debug("\n");
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#endif
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}
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/**
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* Register a new display based on device tree configuration.
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*
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* The frame buffer can be positioned by U-Boot or overriden by the fdt.
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* You should pass in the U-Boot address here, and check the contents of
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* struct tegra_lcd_priv to see what was actually chosen.
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*
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* @param blob Device tree blob
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* @param priv Driver's private data
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* @param default_lcd_base Default address of LCD frame buffer
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* @return 0 if ok, -1 on error (unsupported bits per pixel)
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*/
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static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
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void *default_lcd_base)
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{
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struct disp_ctl_win window;
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struct dc_ctlr *dc;
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priv->frame_buffer = (u32)default_lcd_base;
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dc = (struct dc_ctlr *)priv->disp;
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/*
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* A header file for clock constants was NAKed upstream.
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* TODO: Put this into the FDT and fdt_lcd struct when we have clock
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* support there
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*/
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clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
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144 * 1000000);
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clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
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600 * 1000000);
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basic_init(&dc->cmd);
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basic_init_timer(&dc->disp);
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rgb_enable(&dc->com);
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if (priv->pixel_clock)
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update_display_mode(&dc->disp, priv);
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if (setup_window(&window, priv))
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return -1;
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update_window(dc, &window);
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return 0;
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}
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/**
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* Handle the next stage of device init
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*/
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static int handle_stage(const void *blob, struct tegra_lcd_priv *priv)
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{
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debug("%s: stage %d\n", __func__, priv->stage);
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/* do the things for this stage */
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switch (priv->stage) {
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case STAGE_START:
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/*
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* It is possible that the FDT has requested that the LCD be
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* disabled. We currently don't support this. It would require
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* changes to U-Boot LCD subsystem to have LCD support
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* compiled in but not used. An easier option might be to
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* still have a frame buffer, but leave the backlight off and
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* remove all mention of lcd in the stdout environment
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* variable.
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*/
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funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
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break;
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case STAGE_PANEL_VDD:
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if (dm_gpio_is_valid(&priv->panel_vdd))
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dm_gpio_set_value(&priv->panel_vdd, 1);
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break;
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case STAGE_LVDS:
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if (dm_gpio_is_valid(&priv->lvds_shutdown))
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dm_gpio_set_value(&priv->lvds_shutdown, 1);
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break;
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case STAGE_BACKLIGHT_VDD:
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if (dm_gpio_is_valid(&priv->backlight_vdd))
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dm_gpio_set_value(&priv->backlight_vdd, 1);
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break;
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case STAGE_PWM:
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/* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
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pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
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pinmux_tristate_disable(PMUX_PINGRP_GPU);
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pwm_set_config(priv->pwm, priv->pwm_channel, 0xdf, 0xff);
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pwm_set_enable(priv->pwm, priv->pwm_channel, true);
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break;
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case STAGE_BACKLIGHT_EN:
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if (dm_gpio_is_valid(&priv->backlight_en))
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dm_gpio_set_value(&priv->backlight_en, 1);
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break;
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case STAGE_DONE:
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break;
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}
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/* set up timer for next stage */
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priv->timer_next = timer_get_us();
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if (priv->stage < FDT_LCD_TIMINGS)
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priv->timer_next += priv->panel_timings[priv->stage] * 1000;
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/* move to next stage */
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priv->stage++;
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return 0;
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}
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/**
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* Perform the next stage of the LCD init if it is time to do so.
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*
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* LCD init can be time-consuming because of the number of delays we need
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* while waiting for the backlight power supply, etc. This function can
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* be called at various times during U-Boot operation to advance the
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* initialization of the LCD to the next stage if sufficient time has
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* passed since the last stage. It keeps track of what stage it is up to
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* and the time that it is permitted to move to the next stage.
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*
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* The final call should have wait=1 to complete the init.
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*
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* @param blob fdt blob containing LCD information
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* @param wait 1 to wait until all init is complete, and then return
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* 0 to return immediately, potentially doing nothing if it is
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* not yet time for the next init.
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*/
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static int tegra_lcd_check_next_stage(const void *blob,
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struct tegra_lcd_priv *priv, int wait)
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{
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if (priv->stage == STAGE_DONE)
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return 0;
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do {
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/* wait if we need to */
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debug("%s: stage %d\n", __func__, priv->stage);
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if (priv->stage != STAGE_START) {
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int delay = priv->timer_next - timer_get_us();
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if (delay > 0) {
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if (wait)
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udelay(delay);
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else
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return 0;
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}
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}
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if (handle_stage(blob, priv))
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return -1;
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} while (wait && priv->stage != STAGE_DONE);
|
|
if (priv->stage == STAGE_DONE)
|
|
debug("%s: LCD init complete\n", __func__);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_lcd_probe(struct udevice *dev)
|
|
{
|
|
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
|
|
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
|
|
struct tegra_lcd_priv *priv = dev_get_priv(dev);
|
|
const void *blob = gd->fdt_blob;
|
|
int type = DCACHE_OFF;
|
|
|
|
/* Initialize the Tegra display controller */
|
|
if (tegra_display_probe(blob, priv, (void *)plat->base)) {
|
|
printf("%s: Failed to probe display driver\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
tegra_lcd_check_next_stage(blob, priv, 1);
|
|
|
|
/* Set up the LCD caching as requested */
|
|
if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
|
|
type = DCACHE_WRITETHROUGH;
|
|
else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK)
|
|
type = DCACHE_WRITEBACK;
|
|
mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type);
|
|
|
|
/* Enable flushing after LCD writes if requested */
|
|
video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH);
|
|
|
|
uc_priv->xsize = priv->width;
|
|
uc_priv->ysize = priv->height;
|
|
uc_priv->bpix = priv->log2_bpp;
|
|
debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
|
|
plat->size);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct tegra_lcd_priv *priv = dev_get_priv(dev);
|
|
struct fdtdec_phandle_args args;
|
|
const void *blob = gd->fdt_blob;
|
|
int node = dev->of_offset;
|
|
int front, back, ref;
|
|
int panel_node;
|
|
int rgb;
|
|
int bpp, bit;
|
|
int ret;
|
|
|
|
priv->disp = (struct disp_ctlr *)dev_get_addr(dev);
|
|
if (!priv->disp) {
|
|
debug("%s: No display controller address\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
rgb = fdt_subnode_offset(blob, node, "rgb");
|
|
|
|
panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
|
|
if (panel_node < 0) {
|
|
debug("%s: Cannot find panel information\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->width = fdtdec_get_int(blob, panel_node, "xres", -1);
|
|
priv->height = fdtdec_get_int(blob, panel_node, "yres", -1);
|
|
priv->pixel_clock = fdtdec_get_int(blob, panel_node, "clock", 0);
|
|
if (!priv->pixel_clock || priv->width == -1 || priv->height == -1) {
|
|
debug("%s: Pixel parameters missing\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
back = fdtdec_get_int(blob, panel_node, "left-margin", -1);
|
|
front = fdtdec_get_int(blob, panel_node, "right-margin", -1);
|
|
ref = fdtdec_get_int(blob, panel_node, "hsync-len", -1);
|
|
if ((back | front | ref) == -1) {
|
|
debug("%s: Horizontal parameters missing\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Use a ref-to-sync of 1 always, and take this from the front porch */
|
|
priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
|
|
priv->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
|
|
priv->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
|
|
priv->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
|
|
priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
|
|
debug_timing("horiz", priv->horiz_timing);
|
|
|
|
back = fdtdec_get_int(blob, panel_node, "upper-margin", -1);
|
|
front = fdtdec_get_int(blob, panel_node, "lower-margin", -1);
|
|
ref = fdtdec_get_int(blob, panel_node, "vsync-len", -1);
|
|
if ((back | front | ref) == -1) {
|
|
debug("%s: Vertical parameters missing\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
|
|
priv->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
|
|
priv->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
|
|
priv->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
|
|
priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
|
|
debug_timing("vert", priv->vert_timing);
|
|
|
|
bpp = fdtdec_get_int(blob, panel_node, "nvidia,bits-per-pixel", -1);
|
|
bit = ffs(bpp) - 1;
|
|
if (bpp == (1 << bit))
|
|
priv->log2_bpp = bit;
|
|
else
|
|
priv->log2_bpp = bpp;
|
|
if (bpp == -1) {
|
|
debug("%s: Pixel bpp parameters missing\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (fdtdec_parse_phandle_with_args(blob, panel_node, "nvidia,pwm",
|
|
"#pwm-cells", 0, 0, &args)) {
|
|
debug("%s: Unable to decode PWM\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm);
|
|
if (ret) {
|
|
debug("%s: Unable to find PWM\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
priv->pwm_channel = args.args[0];
|
|
|
|
priv->cache_type = fdtdec_get_int(blob, panel_node, "nvidia,cache-type",
|
|
FDT_LCD_CACHE_WRITE_BACK_FLUSH);
|
|
|
|
/* These GPIOs are all optional */
|
|
gpio_request_by_name_nodev(blob, panel_node,
|
|
"nvidia,backlight-enable-gpios", 0,
|
|
&priv->backlight_en, GPIOD_IS_OUT);
|
|
gpio_request_by_name_nodev(blob, panel_node,
|
|
"nvidia,lvds-shutdown-gpios", 0,
|
|
&priv->lvds_shutdown, GPIOD_IS_OUT);
|
|
gpio_request_by_name_nodev(blob, panel_node,
|
|
"nvidia,backlight-vdd-gpios", 0,
|
|
&priv->backlight_vdd, GPIOD_IS_OUT);
|
|
gpio_request_by_name_nodev(blob, panel_node,
|
|
"nvidia,panel-vdd-gpios", 0,
|
|
&priv->panel_vdd, GPIOD_IS_OUT);
|
|
|
|
if (fdtdec_get_int_array(blob, panel_node, "nvidia,panel-timings",
|
|
priv->panel_timings, FDT_LCD_TIMINGS))
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_lcd_bind(struct udevice *dev)
|
|
{
|
|
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
|
|
const void *blob = gd->fdt_blob;
|
|
int node = dev->of_offset;
|
|
int rgb;
|
|
|
|
rgb = fdt_subnode_offset(blob, node, "rgb");
|
|
if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
|
|
return -ENODEV;
|
|
|
|
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
|
|
(1 << LCD_MAX_LOG2_BPP) / 8;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct video_ops tegra_lcd_ops = {
|
|
};
|
|
|
|
static const struct udevice_id tegra_lcd_ids[] = {
|
|
{ .compatible = "nvidia,tegra20-dc" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(tegra_lcd) = {
|
|
.name = "tegra_lcd",
|
|
.id = UCLASS_VIDEO,
|
|
.of_match = tegra_lcd_ids,
|
|
.ops = &tegra_lcd_ops,
|
|
.bind = tegra_lcd_bind,
|
|
.probe = tegra_lcd_probe,
|
|
.ofdata_to_platdata = tegra_lcd_ofdata_to_platdata,
|
|
.priv_auto_alloc_size = sizeof(struct tegra_lcd_priv),
|
|
};
|