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![Marek Vasut](/assets/img/avatar_default.png)
The set_speed() callback should configure the bus speed, make it so. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
704 lines
16 KiB
C
704 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/global_data.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/spi.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* MX35 and older is CSPI */
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#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35)
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#define MXC_CSPI
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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u32 test;
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};
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#define MXC_CSPICTRL_EN BIT(0)
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#define MXC_CSPICTRL_MODE BIT(1)
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#define MXC_CSPICTRL_XCH BIT(2)
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#define MXC_CSPICTRL_SMC BIT(3)
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#define MXC_CSPICTRL_POL BIT(4)
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#define MXC_CSPICTRL_PHA BIT(5)
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#define MXC_CSPICTRL_SSCTL BIT(6)
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#define MXC_CSPICTRL_SSPOL BIT(7)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_RXOVF BIT(6)
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#define MXC_CSPIPERIOD_32KHZ BIT(15)
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#define MAX_SPI_BYTES 4
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#if defined(CONFIG_MX25) || defined(CONFIG_MX35)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_TC BIT(7)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#else /* MX31 */
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
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#define MXC_CSPICTRL_TC BIT(8)
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#define MXC_CSPICTRL_MAXBITS 0x1f
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#endif
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#else /* MX51 and newer is ECSPI */
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#define MXC_ECSPI
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 cfg;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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};
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#define MXC_CSPICTRL_EN BIT(0)
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#define MXC_CSPICTRL_MODE BIT(1)
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#define MXC_CSPICTRL_XCH BIT(2)
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#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
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#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
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#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPICTRL_TC BIT(7)
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#define MXC_CSPICTRL_RXOVF BIT(6)
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#define MXC_CSPIPERIOD_32KHZ BIT(15)
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#define MAX_SPI_BYTES 32
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/* Bit position inside CTRL register to be associated with SS */
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#define MXC_CSPICTRL_CHAN 18
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/* Bit position inside CON register to be associated with SS */
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#define MXC_CSPICON_PHA 0 /* SCLK phase control */
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#define MXC_CSPICON_POL 4 /* SCLK polarity */
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#define MXC_CSPICON_SSPOL 12 /* SS polarity */
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#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
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#endif
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#ifdef CONFIG_MX27
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/* i.MX27 has a completely wrong register layout and register definitions in the
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* datasheet, the correct one is in the Freescale's Linux driver */
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#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
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"See linux mxc_spi driver from Freescale for details."
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#endif
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__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
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{
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return -1;
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}
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#define OUT MXC_GPIO_DIRECTION_OUT
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#define reg_read readl
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#define reg_write(a, v) writel(v, a)
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#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
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#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
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#endif
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#define MAX_CS_COUNT 4
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struct mxc_spi_slave {
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struct spi_slave slave;
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unsigned long base;
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u32 ctrl_reg;
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#if defined(MXC_ECSPI)
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u32 cfg_reg;
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#endif
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int gpio;
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int ss_pol;
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unsigned int max_hz;
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unsigned int mode;
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struct gpio_desc ss;
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struct gpio_desc cs_gpios[MAX_CS_COUNT];
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struct udevice *dev;
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};
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static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
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{
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return container_of(slave, struct mxc_spi_slave, slave);
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}
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static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
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{
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#if CONFIG_IS_ENABLED(DM_SPI)
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struct udevice *dev = mxcs->dev;
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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u32 cs = slave_plat->cs;
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if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
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return;
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dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
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#else
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if (mxcs->gpio > 0)
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gpio_set_value(mxcs->gpio, mxcs->ss_pol);
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#endif
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}
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static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
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{
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#if CONFIG_IS_ENABLED(DM_SPI)
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struct udevice *dev = mxcs->dev;
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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u32 cs = slave_plat->cs;
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if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
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return;
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dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
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#else
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if (mxcs->gpio > 0)
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gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
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#endif
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}
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u32 get_cspi_div(u32 div)
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{
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int i;
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for (i = 0; i < 8; i++) {
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if (div <= (4 << i))
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return i;
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}
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return i;
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}
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#ifdef MXC_CSPI
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static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
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{
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unsigned int ctrl_reg;
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u32 clk_src;
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u32 div;
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unsigned int max_hz = mxcs->max_hz;
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unsigned int mode = mxcs->mode;
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clk_src = mxc_get_clock(MXC_CSPI_CLK);
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div = DIV_ROUND_UP(clk_src, max_hz);
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div = get_cspi_div(div);
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debug("clk %d Hz, div %d, real clk %d Hz\n",
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max_hz, div, clk_src / (4 << div));
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ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
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MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
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MXC_CSPICTRL_DATARATE(div) |
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MXC_CSPICTRL_EN |
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#ifdef CONFIG_MX35
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MXC_CSPICTRL_SSCTL |
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#endif
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MXC_CSPICTRL_MODE;
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if (mode & SPI_CPHA)
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ctrl_reg |= MXC_CSPICTRL_PHA;
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if (mode & SPI_CPOL)
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ctrl_reg |= MXC_CSPICTRL_POL;
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if (mode & SPI_CS_HIGH)
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ctrl_reg |= MXC_CSPICTRL_SSPOL;
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mxcs->ctrl_reg = ctrl_reg;
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return 0;
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}
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#endif
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#ifdef MXC_ECSPI
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static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
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{
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u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
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s32 reg_ctrl, reg_config;
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u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
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u32 pre_div = 0, post_div = 0;
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struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
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unsigned int max_hz = mxcs->max_hz;
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unsigned int mode = mxcs->mode;
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/*
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* Reset SPI and set all CSs to master mode, if toggling
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* between slave and master mode we might see a glitch
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* on the clock line
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*/
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reg_ctrl = MXC_CSPICTRL_MODE_MASK;
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reg_write(®s->ctrl, reg_ctrl);
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reg_ctrl |= MXC_CSPICTRL_EN;
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reg_write(®s->ctrl, reg_ctrl);
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if (clk_src > max_hz) {
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pre_div = (clk_src - 1) / max_hz;
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/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
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post_div = fls(pre_div);
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if (post_div > 4) {
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post_div -= 4;
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if (post_div >= 16) {
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printf("Error: no divider for the freq: %d\n",
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max_hz);
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return -1;
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}
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pre_div >>= post_div;
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} else {
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post_div = 0;
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}
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}
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debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
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reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
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MXC_CSPICTRL_SELCHAN(cs);
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reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
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MXC_CSPICTRL_PREDIV(pre_div);
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reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
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MXC_CSPICTRL_POSTDIV(post_div);
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if (mode & SPI_CS_HIGH)
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ss_pol = 1;
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if (mode & SPI_CPOL) {
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sclkpol = 1;
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sclkctl = 1;
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}
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if (mode & SPI_CPHA)
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sclkpha = 1;
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reg_config = reg_read(®s->cfg);
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/*
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* Configuration register setup
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* The MX51 supports different setup for each SS
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*/
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
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(ss_pol << (cs + MXC_CSPICON_SSPOL));
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
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(sclkpol << (cs + MXC_CSPICON_POL));
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
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(sclkctl << (cs + MXC_CSPICON_CTL));
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
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(sclkpha << (cs + MXC_CSPICON_PHA));
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debug("reg_ctrl = 0x%x\n", reg_ctrl);
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reg_write(®s->ctrl, reg_ctrl);
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debug("reg_config = 0x%x\n", reg_config);
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reg_write(®s->cfg, reg_config);
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/* save config register and control register */
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mxcs->ctrl_reg = reg_ctrl;
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mxcs->cfg_reg = reg_config;
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/* clear interrupt reg */
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reg_write(®s->intr, 0);
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reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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return 0;
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}
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#endif
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int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
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const u8 *dout, u8 *din, unsigned long flags)
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{
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int nbytes = DIV_ROUND_UP(bitlen, 8);
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u32 data, cnt, i;
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struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
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u32 ts;
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int status;
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debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
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__func__, bitlen, (ulong)dout, (ulong)din);
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mxcs->ctrl_reg = (mxcs->ctrl_reg &
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~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
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MXC_CSPICTRL_BITCOUNT(bitlen - 1);
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reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
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#ifdef MXC_ECSPI
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reg_write(®s->cfg, mxcs->cfg_reg);
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#endif
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/* Clear interrupt register */
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reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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/*
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* The SPI controller works only with words,
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* check if less than a word is sent.
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* Access to the FIFO is only 32 bit
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*/
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if (bitlen % 32) {
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data = 0;
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cnt = (bitlen % 32) / 8;
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if (dout) {
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for (i = 0; i < cnt; i++) {
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data = (data << 8) | (*dout++ & 0xFF);
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}
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}
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debug("Sending SPI 0x%x\n", data);
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reg_write(®s->txdata, data);
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nbytes -= cnt;
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}
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data = 0;
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while (nbytes > 0) {
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data = 0;
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if (dout) {
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/* Buffer is not 32-bit aligned */
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if ((unsigned long)dout & 0x03) {
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data = 0;
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for (i = 0; i < 4; i++)
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data = (data << 8) | (*dout++ & 0xFF);
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} else {
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data = *(u32 *)dout;
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data = cpu_to_be32(data);
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dout += 4;
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}
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}
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debug("Sending SPI 0x%x\n", data);
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reg_write(®s->txdata, data);
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nbytes -= 4;
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}
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/* FIFO is written, now starts the transfer setting the XCH bit */
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reg_write(®s->ctrl, mxcs->ctrl_reg |
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MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
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ts = get_timer(0);
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status = reg_read(®s->stat);
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/* Wait until the TC (Transfer completed) bit is set */
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while ((status & MXC_CSPICTRL_TC) == 0) {
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if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
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printf("spi_xchg_single: Timeout!\n");
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return -1;
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}
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status = reg_read(®s->stat);
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}
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/* Transfer completed, clear any pending request */
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reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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nbytes = DIV_ROUND_UP(bitlen, 8);
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cnt = nbytes % 32;
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if (bitlen % 32) {
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data = reg_read(®s->rxdata);
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cnt = (bitlen % 32) / 8;
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data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
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debug("SPI Rx unaligned: 0x%x\n", data);
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if (din) {
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memcpy(din, &data, cnt);
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din += cnt;
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}
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nbytes -= cnt;
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}
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while (nbytes > 0) {
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u32 tmp;
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tmp = reg_read(®s->rxdata);
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data = cpu_to_be32(tmp);
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debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
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cnt = min_t(u32, nbytes, sizeof(data));
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if (din) {
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memcpy(din, &data, cnt);
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din += cnt;
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}
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nbytes -= cnt;
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}
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return 0;
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}
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static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
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unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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int n_bytes = DIV_ROUND_UP(bitlen, 8);
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int n_bits;
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int ret;
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u32 blk_size;
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u8 *p_outbuf = (u8 *)dout;
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u8 *p_inbuf = (u8 *)din;
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if (!mxcs)
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return -EINVAL;
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if (flags & SPI_XFER_BEGIN)
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mxc_spi_cs_activate(mxcs);
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while (n_bytes > 0) {
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if (n_bytes < MAX_SPI_BYTES)
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blk_size = n_bytes;
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else
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blk_size = MAX_SPI_BYTES;
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n_bits = blk_size * 8;
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ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
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if (ret)
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return ret;
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if (dout)
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p_outbuf += blk_size;
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if (din)
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p_inbuf += blk_size;
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n_bytes -= blk_size;
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}
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if (flags & SPI_XFER_END) {
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mxc_spi_cs_deactivate(mxcs);
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}
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return 0;
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}
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static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
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{
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struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
|
|
int ret;
|
|
|
|
reg_write(®s->rxdata, 1);
|
|
udelay(1);
|
|
ret = spi_cfg_mxc(mxcs, cs);
|
|
if (ret) {
|
|
printf("mxc_spi: cannot setup SPI controller\n");
|
|
return ret;
|
|
}
|
|
reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
|
|
reg_write(®s->intr, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if !CONFIG_IS_ENABLED(DM_SPI)
|
|
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
|
|
void *din, unsigned long flags)
|
|
{
|
|
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
|
|
|
|
return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
|
|
}
|
|
|
|
/*
|
|
* Some SPI devices require active chip-select over multiple
|
|
* transactions, we achieve this using a GPIO. Still, the SPI
|
|
* controller has to be configured to use one of its own chipselects.
|
|
* To use this feature you have to implement board_spi_cs_gpio() to assign
|
|
* a gpio value for each cs (-1 if cs doesn't need to use gpio).
|
|
* You must use some unused on this SPI controller cs between 0 and 3.
|
|
*/
|
|
static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
|
|
unsigned int bus, unsigned int cs)
|
|
{
|
|
int ret;
|
|
|
|
mxcs->gpio = board_spi_cs_gpio(bus, cs);
|
|
if (mxcs->gpio == -1)
|
|
return 0;
|
|
|
|
gpio_request(mxcs->gpio, "spi-cs");
|
|
ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
|
|
if (ret) {
|
|
printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long spi_bases[] = {
|
|
MXC_SPI_BASE_ADDRESSES
|
|
};
|
|
|
|
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
|
|
unsigned int max_hz, unsigned int mode)
|
|
{
|
|
struct mxc_spi_slave *mxcs;
|
|
int ret;
|
|
|
|
if (bus >= ARRAY_SIZE(spi_bases))
|
|
return NULL;
|
|
|
|
if (max_hz == 0) {
|
|
printf("Error: desired clock is 0\n");
|
|
return NULL;
|
|
}
|
|
|
|
mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
|
|
if (!mxcs) {
|
|
puts("mxc_spi: SPI Slave not allocated !\n");
|
|
return NULL;
|
|
}
|
|
|
|
mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
|
|
|
|
ret = setup_cs_gpio(mxcs, bus, cs);
|
|
if (ret < 0) {
|
|
free(mxcs);
|
|
return NULL;
|
|
}
|
|
|
|
mxcs->base = spi_bases[bus];
|
|
mxcs->max_hz = max_hz;
|
|
mxcs->mode = mode;
|
|
|
|
return &mxcs->slave;
|
|
}
|
|
|
|
void spi_free_slave(struct spi_slave *slave)
|
|
{
|
|
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
|
|
|
|
free(mxcs);
|
|
}
|
|
|
|
int spi_claim_bus(struct spi_slave *slave)
|
|
{
|
|
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
|
|
|
|
return mxc_spi_claim_bus_internal(mxcs, slave->cs);
|
|
}
|
|
|
|
void spi_release_bus(struct spi_slave *slave)
|
|
{
|
|
/* TODO: Shut the controller down */
|
|
}
|
|
#else
|
|
|
|
static int mxc_spi_probe(struct udevice *bus)
|
|
{
|
|
struct mxc_spi_slave *mxcs = dev_get_plat(bus);
|
|
int node = dev_of_offset(bus);
|
|
const void *blob = gd->fdt_blob;
|
|
int ret;
|
|
int i;
|
|
|
|
ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
|
|
ARRAY_SIZE(mxcs->cs_gpios), 0);
|
|
if (ret < 0) {
|
|
pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
|
|
if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
|
|
continue;
|
|
|
|
ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
|
|
GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
|
|
if (ret) {
|
|
dev_err(bus, "Setting cs %d error\n", i);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
mxcs->base = dev_read_addr(bus);
|
|
if (mxcs->base == FDT_ADDR_T_NONE)
|
|
return -ENODEV;
|
|
|
|
#if CONFIG_IS_ENABLED(CLK)
|
|
struct clk clk;
|
|
ret = clk_get_by_index(bus, 0, &clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
clk_enable(&clk);
|
|
|
|
mxcs->max_hz = clk_get_rate(&clk);
|
|
#else
|
|
mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
|
|
20000000);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
|
const void *dout, void *din, unsigned long flags)
|
|
{
|
|
struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
|
|
|
|
|
|
return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
|
|
}
|
|
|
|
static int mxc_spi_claim_bus(struct udevice *dev)
|
|
{
|
|
struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
|
|
struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
|
|
|
|
mxcs->dev = dev;
|
|
|
|
return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
|
|
}
|
|
|
|
static int mxc_spi_release_bus(struct udevice *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int mxc_spi_set_speed(struct udevice *bus, uint speed)
|
|
{
|
|
struct mxc_spi_slave *mxcs = dev_get_plat(bus);
|
|
|
|
mxcs->max_hz = speed;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mxc_spi_set_mode(struct udevice *bus, uint mode)
|
|
{
|
|
struct mxc_spi_slave *mxcs = dev_get_plat(bus);
|
|
|
|
mxcs->mode = mode;
|
|
mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_spi_ops mxc_spi_ops = {
|
|
.claim_bus = mxc_spi_claim_bus,
|
|
.release_bus = mxc_spi_release_bus,
|
|
.xfer = mxc_spi_xfer,
|
|
.set_speed = mxc_spi_set_speed,
|
|
.set_mode = mxc_spi_set_mode,
|
|
};
|
|
|
|
static const struct udevice_id mxc_spi_ids[] = {
|
|
{ .compatible = "fsl,imx51-ecspi" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(mxc_spi) = {
|
|
.name = "mxc_spi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = mxc_spi_ids,
|
|
.ops = &mxc_spi_ops,
|
|
.plat_auto = sizeof(struct mxc_spi_slave),
|
|
.probe = mxc_spi_probe,
|
|
};
|
|
#endif
|