mirror of
https://github.com/brain-hackers/u-boot-brain
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2d8db6d315
Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
32 lines
732 B
C
32 lines
732 B
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_SECURE_BOOT_H
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#define __FSL_SECURE_BOOT_H
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#ifdef CONFIG_SECURE_BOOT
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#if defined(CONFIG_FSL_CORENET)
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#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
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#elif defined(CONFIG_BSC9132QDS)
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#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
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#else
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#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
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#endif
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#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
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#if defined(CONFIG_B4860QDS) || \
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defined(CONFIG_T4240QDS) || \
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defined(CONFIG_T2080QDS) || \
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defined(CONFIG_T1040QDS) || \
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defined(CONFIG_T1040RDB)
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#define CONFIG_SYS_CPC_REINIT_F
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#undef CONFIG_SYS_INIT_L3_ADDR
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#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
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#endif
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#endif
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#endif
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