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c346cf1350
The OpenRISC architecture specification v1.0 defines new SPR registers. This patch adds registers definition for group 0 and update bit definitions for the CPU configuration register. Signed-off-by: Franck Jullien <franck.jullien@gmail.com> |
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arc | ||
arm | ||
avr32 | ||
blackfin | ||
m68k | ||
microblaze | ||
mips | ||
nds32 | ||
nios2 | ||
openrisc | ||
powerpc | ||
sandbox | ||
sh | ||
sparc | ||
x86 | ||
.gitignore |