mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
255 lines
6.3 KiB
C
255 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <hwconfig.h>
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#include <asm/mmu.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <asm/fsl_law.h>
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#include <asm/mpc85xx_gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 rank_gb;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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};
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/*
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* datarate_mhz_high values need to be in ascending order
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
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*/
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{2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
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{2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
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{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
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{1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
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{1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
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{1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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struct cpu_type *cpu = gd->arch.cpu;
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if (ctrl_num > 1) {
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printf("Not supported controller number %d\n", ctrl_num);
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return;
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}
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if (!pdimm->n_ranks)
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return;
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pbsp = udimms[0];
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/* Get clk_adjust according to the board ddr freqency and n_banks
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* specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm->n_ranks &&
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(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->wrlvl_start = pbsp->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found\n");
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printf("for data rate %lu MT/s\n", ddr_freq);
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printf("Trying to use the highest speed (%u) parameters\n",
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pbsp_highest->datarate_mhz_high);
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popts->clk_adjust = pbsp_highest->clk_adjust;
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popts->wrlvl_start = pbsp_highest->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
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pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
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debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
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pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
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debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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/*
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* Write leveling override
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*/
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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/*
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* rtt and rtt_wr override
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*/
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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/* DHC_EN =1, ODT = 75 Ohm */
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
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/* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
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* force DDR bus width to 32bit for T1023
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*/
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if (cpu->soc_ver == SVR_T1023)
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popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
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#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
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/* for DDR bus 32bit test on T1024 */
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popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
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#endif
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#ifdef CONFIG_TARGET_T1023RDB
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popts->wrlvl_ctl_2 = 0x07070606;
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popts->half_strength_driver_enable = 1;
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popts->cpo_sample = 0x43;
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#elif defined(CONFIG_TARGET_T1024RDB)
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/* optimize cpo for erratum A-009942 */
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popts->cpo_sample = 0x52;
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#endif
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}
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#ifdef CONFIG_SYS_DDR_RAW_TIMING
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/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 1,
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.rank_density = 0x80000000,
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.capacity = 0x80000000,
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.primary_sdram_width = 32,
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.ec_sdram_width = 8,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 15,
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.n_col_addr = 10,
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.bank_addr_bits = 2,
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.bank_group_bits = 2,
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.edc_config = 0,
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.burst_lengths_bitmask = 0x0c,
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.tckmin_x_ps = 938,
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.tckmax_ps = 1500,
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.caslat_x = 0x000DFA00,
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.taa_ps = 13500,
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.trcd_ps = 13500,
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.trp_ps = 13500,
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.tras_ps = 33000,
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.trc_ps = 46500,
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.trfc1_ps = 260000,
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.trfc2_ps = 160000,
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.trfc4_ps = 110000,
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.tfaw_ps = 25000,
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.trrds_ps = 3700,
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.trrdl_ps = 5300,
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.tccdl_ps = 5355,
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.refresh_rate_ps = 7800000,
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.dq_mapping[0] = 0x0,
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.dq_mapping[1] = 0x0,
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.dq_mapping[2] = 0x0,
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.dq_mapping[3] = 0x0,
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.dq_mapping[4] = 0x0,
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.dq_mapping[5] = 0x0,
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.dq_mapping[6] = 0x0,
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.dq_mapping[7] = 0x0,
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.dq_mapping[8] = 0x0,
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.dq_mapping[9] = 0x0,
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.dq_mapping[10] = 0x0,
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.dq_mapping[11] = 0x0,
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.dq_mapping[12] = 0x0,
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.dq_mapping[13] = 0x0,
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.dq_mapping[14] = 0x0,
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.dq_mapping[15] = 0x0,
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.dq_mapping[16] = 0x0,
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.dq_mapping[17] = 0x0,
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.dq_mapping_ors = 1,
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};
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int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
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unsigned int controller_number,
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unsigned int dimm_number)
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{
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const char dimm_model[] = "Fixed DDR4 on board";
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if (((controller_number == 0) && (dimm_number == 0)) ||
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((controller_number == 1) && (dimm_number == 0))) {
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memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
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memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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}
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return 0;
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}
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#endif
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#if defined(CONFIG_DEEP_SLEEP)
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void board_mem_sleep_setup(void)
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{
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void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
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/* does not provide HW signals for power management */
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clrbits_8(cpld_base + 0x17, 0x40);
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/* Disable MCKE isolation */
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gpio_set_value(2, 0);
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udelay(1);
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}
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#endif
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int dram_init(void)
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{
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phys_size_t dram_size;
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#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
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#ifndef CONFIG_SYS_DDR_RAW_TIMING
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puts("Initializing....using SPD\n");
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#endif
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dram_size = fsl_ddr_sdram();
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#else
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/* DDR has been initialised by first stage boot loader */
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dram_size = fsl_ddr_sdram_size();
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#endif
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
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fsl_dp_resume();
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#endif
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gd->ram_size = dram_size;
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return 0;
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}
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