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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
156 lines
4.7 KiB
C
156 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*/
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/*
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* Generic driver for Freescale MMDC(Multi Mode DDR Controller).
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*/
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#include <common.h>
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#include <fsl_mmdc.h>
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#include <asm/io.h>
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static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
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{
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int timeout = 1000;
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out_be32(ptr, value);
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while (in_be32(ptr) & bits) {
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udelay(100);
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timeout--;
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}
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if (timeout <= 0)
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printf("Error: %p wait for clear timeout.\n", ptr);
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}
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void mmdc_init(const struct fsl_mmdc_info *priv)
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{
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struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
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unsigned int tmp;
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/* 1. set configuration request */
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out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
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/* 2. configure the desired timing parameters */
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out_be32(&mmdc->mdotc, priv->mdotc);
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out_be32(&mmdc->mdcfg0, priv->mdcfg0);
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out_be32(&mmdc->mdcfg1, priv->mdcfg1);
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out_be32(&mmdc->mdcfg2, priv->mdcfg2);
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/* 3. configure DDR type and other miscellaneous parameters */
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out_be32(&mmdc->mdmisc, priv->mdmisc);
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out_be32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR);
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out_be32(&mmdc->mdrwd, priv->mdrwd);
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out_be32(&mmdc->mpodtctrl, priv->mpodtctrl);
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/* 4. configure the required delay while leaving reset */
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out_be32(&mmdc->mdor, priv->mdor);
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/* 5. configure DDR physical parameters */
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/* set row/column address width, burst length, data bus width */
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tmp = priv->mdctl & ~(MDCTL_SDE0 | MDCTL_SDE1);
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out_be32(&mmdc->mdctl, tmp);
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/* configure address space partition */
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out_be32(&mmdc->mdasp, priv->mdasp);
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/* 6. perform a ZQ calibration - not needed here, doing in #8b */
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/* 7. enable MMDC with the desired chip select */
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#if (CONFIG_CHIP_SELECTS_PER_CTRL == 1)
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out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0);
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#elif (CONFIG_CHIP_SELECTS_PER_CTRL == 2)
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out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);
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#endif
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/* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2);
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0) | MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
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out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x19) |
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CMD_ADDR_LSB_MR_ADDR(0x30) |
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MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0);
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/* 8b. ZQ calibration */
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out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x4) | MDSCR_ENABLE_CON_REQ |
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CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0);
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set_wait_for_bits_clear(&mmdc->mpzqhwctrl, priv->mpzqhwctrl,
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MPZQHWCTRL_ZQ_HW_FORCE);
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/* 9a. calibrations now, wr lvl */
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0x84) |
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MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
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out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN |
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CMD_NORMAL);
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set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,
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MPWLGCR_HW_WL_EN);
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mdelay(1);
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
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out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
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mdelay(1);
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/* 9b. read DQS gating calibration */
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out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
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out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
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/* set absolute read delay offset */
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if (priv->mprddlctl)
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out_be32(&mmdc->mprddlctl, priv->mprddlctl);
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else
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out_be32(&mmdc->mprddlctl, MMDC_MPRDDLCTL_DEFAULT_DELAY);
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set_wait_for_bits_clear(&mmdc->mpdgctrl0,
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AUTO_RD_DQS_GATING_CALIBRATION_EN,
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AUTO_RD_DQS_GATING_CALIBRATION_EN);
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out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3);
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/* 9c. read calibration */
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out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
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CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
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out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
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CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
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out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
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set_wait_for_bits_clear(&mmdc->mprddlhwctl,
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MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN,
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MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN);
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out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
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CMD_BANK_ADDR_3);
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/* 10. configure power-down, self-refresh entry, exit parameters */
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out_be32(&mmdc->mdpdc, priv->mdpdc);
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out_be32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT);
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/* 11. ZQ config again? do nothing here */
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/* 12. refresh scheme */
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set_wait_for_bits_clear(&mmdc->mdref, priv->mdref,
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MDREF_START_REFRESH);
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/* 13. disable CON_REQ */
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out_be32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ);
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}
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