mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 04:36:16 +09:00
a0aba8a2eb
CONFIG_SYS_[DI]CACHE_OFF had been partially converted to Kconfig
parameters; only for the ARC architecture. This patch turns these two
parameters into Kconfig items everywhere else they are found.
All of the include/configs/* and defconfig changes in this patch are
for arm machines only. The Kconfig changes for arc, nds32, riscv,
and xtensa have been included since these symbols are found in code
under arch/{arc,nds32,riscv,xtensa}, however, no currently-defined
include/configs/* or defconfigs for these architectures exist which
include these symbols.
These results have been confirmed with tools/moveconfig.py.
Acked-by: Alexey Brodkin <abrodkin@snopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Re-migrate for a few more boards]
Signed-off-by: Tom Rini <trini@konsulko.com>
186 lines
4.6 KiB
C
186 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Toradex Colibri PXA270 configuration file
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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* Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Board Configuration Options
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*/
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#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
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/* Avoid overwriting factory configuration block */
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#define CONFIG_BOARD_SIZE_LIMIT 0x40000
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_BOOTCOMMAND \
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"if fatload mmc 0 0xa0000000 uImage; then " \
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"bootm 0xa0000000; " \
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"fi; " \
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"if usb reset && fatload usb 0 0xa0000000 uImage; then " \
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"bootm 0xa0000000; " \
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"fi; " \
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"bootm 0xc0000;"
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#define CONFIG_TIMESTAMP
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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/*
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* Serial Console Configuration
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*/
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/*
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* Bootloader Components Configuration
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*/
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/* I2C support */
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#ifdef CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_PXA
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#define CONFIG_PXA_STD_I2C
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#define CONFIG_PXA_PWR_I2C
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#define CONFIG_SYS_I2C_SPEED 100000
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#endif
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/* LCD support */
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#ifdef CONFIG_LCD
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#define CONFIG_PXA_LCD
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#define CONFIG_PXA_VGA
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#define CONFIG_LCD_LOGO
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#endif
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/*
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* Networking Configuration
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*/
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#ifdef CONFIG_CMD_NET
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#define CONFIG_DRIVER_DM9000 1
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#define CONFIG_DM9000_BASE 0x08000000
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#define DM9000_IO (CONFIG_DM9000_BASE)
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#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
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#define CONFIG_NET_RETRY_COUNT 10
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#define CONFIG_BOOTP_BOOTFILESIZE
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#endif
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#define CONFIG_SYS_DEVICE_NULLDEV 1
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/*
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* Clock Configuration
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*/
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#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
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/*
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* DRAM Map
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*/
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
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#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
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#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
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/*
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* NOR FLASH
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*/
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#ifdef CONFIG_CMD_FLASH
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
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#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ)
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#endif
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#define CONFIG_SYS_MONITOR_BASE 0x0
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#define CONFIG_SYS_MONITOR_LEN 0x40000
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/* Skip factory configuration block */
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
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#define CONFIG_ENV_SIZE 0x40000
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#define CONFIG_ENV_SECT_SIZE 0x40000
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/*
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* GPIO settings
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*/
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#define CONFIG_SYS_GPSR0_VAL 0x00000000
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#define CONFIG_SYS_GPSR1_VAL 0x00020000
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#define CONFIG_SYS_GPSR2_VAL 0x0002c000
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#define CONFIG_SYS_GPSR3_VAL 0x00000000
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#define CONFIG_SYS_GPCR0_VAL 0x00000000
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#define CONFIG_SYS_GPCR1_VAL 0x00000000
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#define CONFIG_SYS_GPCR2_VAL 0x00000000
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#define CONFIG_SYS_GPCR3_VAL 0x00000000
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#define CONFIG_SYS_GPDR0_VAL 0xc8008000
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#define CONFIG_SYS_GPDR1_VAL 0xfc02a981
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#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
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#define CONFIG_SYS_GPDR3_VAL 0x0061e804
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#define CONFIG_SYS_GAFR0_L_VAL 0x80100000
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#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
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#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
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#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
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#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
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#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
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#define CONFIG_SYS_GAFR3_L_VAL 0x54000310
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#define CONFIG_SYS_GAFR3_U_VAL 0x00005401
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#define CONFIG_SYS_PSSR_VAL 0x30
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/*
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* Clock settings
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*/
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#define CONFIG_SYS_CKEN 0x00500240
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#define CONFIG_SYS_CCCR 0x02000290
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/*
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* Memory settings
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*/
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#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
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#define CONFIG_SYS_MSC1_VAL 0x9ee1f994
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#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
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#define CONFIG_SYS_MDCNFG_VAL 0x090009c9
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#define CONFIG_SYS_MDREFR_VAL 0x2003a031
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#define CONFIG_SYS_MDMRS_VAL 0x00220022
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#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
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#define CONFIG_SYS_SXCNFG_VAL 0x40044004
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/*
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* PCMCIA and CF Interfaces
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*/
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#define CONFIG_SYS_MECR_VAL 0x00000000
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#define CONFIG_SYS_MCMEM0_VAL 0x00028307
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#define CONFIG_SYS_MCMEM1_VAL 0x00014307
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#define CONFIG_SYS_MCATT0_VAL 0x00038787
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#define CONFIG_SYS_MCATT1_VAL 0x0001c787
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#define CONFIG_SYS_MCIO0_VAL 0x0002830f
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#define CONFIG_SYS_MCIO1_VAL 0x0001430f
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#include "pxa-common.h"
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#endif /* __CONFIG_H */
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