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https://github.com/brain-hackers/u-boot-brain
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20187fd11c
This patch adds Keystone2 K2E SOC specific code to support MSMC cache coherency. Also create header file for msmc to hold its API. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
68 lines
1.4 KiB
C
68 lines
1.4 KiB
C
/*
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* Keystone2: Architecture initialization
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ns16550.h>
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#include <asm/io.h>
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#include <asm/arch/msmc.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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void chip_configuration_unlock(void)
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{
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__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
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__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
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}
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int arch_cpu_init(void)
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{
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chip_configuration_unlock();
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icache_enable();
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msmc_share_all_segments(8); /* TETRIS */
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msmc_share_all_segments(9); /* NETCP */
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msmc_share_all_segments(10); /* QM PDSP */
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msmc_share_all_segments(11); /* PCIE 0 */
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#ifdef CONFIG_SOC_K2E
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msmc_share_all_segments(13); /* PCIE 1 */
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#endif
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/*
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* just initialise the COM2 port so that TI specific
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* UART register PWREMU_MGMT is initialized. Linux UART
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* driver doesn't handle this.
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*/
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NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
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CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
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u32 tmp;
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tmp = *rstctrl & KS2_RSTCTRL_MASK;
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*rstctrl = tmp | KS2_RSTCTRL_KEY;
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*rstctrl &= KS2_RSTCTRL_SWRST;
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for (;;)
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;
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}
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void enable_caches(void)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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#endif
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}
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