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https://github.com/brain-hackers/u-boot-brain
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3d31538625
Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and add KS2_ prefix where it's needed. It requires to change names also in places where they're used. Align lines and remove redundant definitions in kardware-k2hk.h at the same time. Using common KS2_ prefix helps resolve redundant redefinitions and adds opportunity to use KS2_ definition across a project not thinking about what SoC should be used. It's more convenient and we don't need to worry about the SoC type in common files, hardware.h will think about that. The hardware.h decides definitions of what SoC to use. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
89 lines
2.8 KiB
C
89 lines
2.8 KiB
C
/*
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* Keystone2: DDR3 initialization
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <asm/arch/ddr3.h>
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void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
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{
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unsigned int tmp;
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while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
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& 0x00000001) != 0x00000001)
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;
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__raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
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tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
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tmp &= ~(phy_cfg->pgcr1_mask);
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tmp |= phy_cfg->pgcr1_val;
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__raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
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__raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET);
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__raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET);
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__raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET);
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__raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET);
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tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
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tmp &= ~(phy_cfg->dcr_mask);
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tmp |= phy_cfg->dcr_val;
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__raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
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__raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
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__raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
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__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
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__raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
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__raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
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__raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
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__raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
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__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
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__raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
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__raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
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__raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
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__raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
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while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
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;
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__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
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while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
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;
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}
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void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
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{
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__raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
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__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
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__raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
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__raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
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__raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
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__raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
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__raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
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}
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void ddr3_reset_ddrphy(void)
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{
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u32 tmp;
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/* Assert DDR3A PHY reset */
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tmp = readl(KS2_DDR3APLLCTL1);
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tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
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writel(tmp, KS2_DDR3APLLCTL1);
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/* wait 10us to catch the reset */
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udelay(10);
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/* Release DDR3A PHY reset */
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tmp = readl(KS2_DDR3APLLCTL1);
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tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
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__raw_writel(tmp, KS2_DDR3APLLCTL1);
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}
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