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https://github.com/brain-hackers/u-boot-brain
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e9024ef27d
Add the SATA boot support for OMAP5 and dra7xx. Renamed the omap_sata_init to the common init_sata(int dev) for commonality in with sata stack. Added the ROM boot device ID for SATA. Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
77 lines
1.7 KiB
C
77 lines
1.7 KiB
C
/*
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* TI SATA platform driver
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*
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* (C) Copyright 2013
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* Texas Instruments, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sata.h>
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#include <sata.h>
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#include <asm/io.h>
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#include "pipe3-phy.h"
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static struct pipe3_dpll_map dpll_map_sata[] = {
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{12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
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{16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
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{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
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{20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
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{26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
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{38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
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{ }, /* Terminator */
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};
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struct omap_pipe3 sata_phy = {
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.pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
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/* .power_reg is updated at runtime */
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.dpll_map = dpll_map_sata,
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};
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int init_sata(int dev)
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{
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int ret;
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u32 val;
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u32 const clk_domains_sata[] = {
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0
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};
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u32 const clk_modules_hw_auto_sata[] = {
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(*prcm)->cm_l3init_ocp2scp3_clkctrl,
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0
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};
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u32 const clk_modules_explicit_en_sata[] = {
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(*prcm)->cm_l3init_sata_clkctrl,
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0
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};
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do_enable_clocks(clk_domains_sata,
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clk_modules_hw_auto_sata,
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clk_modules_explicit_en_sata,
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0);
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/* Enable optional functional clock for SATA */
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setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
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SATA_CLKCTRL_OPTFCLKEN_MASK);
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sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
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/* Power up the PHY */
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phy_pipe3_power_on(&sata_phy);
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/* Enable SATA module, No Idle, No Standby */
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val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
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writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
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ret = ahci_init(DWC_AHSATA_BASE);
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scsi_scan(1);
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return ret;
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}
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