mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-24 20:09:43 +09:00
734af242c2
gpmc timeout is disabled and the reset counter is set to 0. However, if later a driver activates the timeout setting the reset to a valid value, the old reset value with zero is still valid for the first access. In fact, the timeout block loads the reset counter after a successful access. Found on a am335x board with a FPGA connected to the GPMC bus together with the NAND. When the FPGA driver in kernel activates the timeout, the system hangs at the first access by the NAND driver. Signed-off-by: Stefano Babic <sbabic@denx.de>
140 lines
3.8 KiB
C
140 lines
3.8 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Mansoor Ahamed <mansoor.ahamed@ti.com>
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*
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* Initial Code from:
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* Manikandan Pillai <mani.pillai@ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <command.h>
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#include <linux/mtd/omap_gpmc.h>
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struct gpmc *gpmc_cfg;
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#if defined(CONFIG_OMAP34XX)
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/********************************************************
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* mem_ok() - test used to see if timings are correct
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* for a part. Helps in guessing which part
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* we are currently using.
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*******************************************************/
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u32 mem_ok(u32 cs)
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{
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u32 val1, val2, addr;
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u32 pattern = 0x12345678;
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addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
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writel(0x0, addr + 0x400); /* clear pos A */
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writel(pattern, addr); /* pattern to pos B */
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writel(0x0, addr + 4); /* remove pattern off the bus */
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val1 = readl(addr + 0x400); /* get pos A value */
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val2 = readl(addr); /* get val2 */
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writel(0x0, addr + 0x400); /* clear pos A */
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if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
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return 0;
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else
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return 1;
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}
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#endif
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void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
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u32 size)
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{
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writel(0, &cs->config7);
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sdelay(1000);
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/* Delay for settling */
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writel(gpmc_config[0], &cs->config1);
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writel(gpmc_config[1], &cs->config2);
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writel(gpmc_config[2], &cs->config3);
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writel(gpmc_config[3], &cs->config4);
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writel(gpmc_config[4], &cs->config5);
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writel(gpmc_config[5], &cs->config6);
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/* Enable the config */
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writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
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(1 << 6)), &cs->config7);
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sdelay(2000);
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}
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/*****************************************************
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* gpmc_init(): init gpmc bus
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* Init GPMC for x16, MuxMode (SDRAM in x32).
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* This code can only be executed from SRAM or SDRAM.
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*****************************************************/
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void gpmc_init(void)
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{
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/* putting a blanket check on GPMC based on ZeBu for now */
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gpmc_cfg = (struct gpmc *)GPMC_BASE;
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#if defined(CONFIG_NOR)
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/* configure GPMC for NOR */
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const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
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STNOR_GPMC_CONFIG2,
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STNOR_GPMC_CONFIG3,
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STNOR_GPMC_CONFIG4,
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STNOR_GPMC_CONFIG5,
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STNOR_GPMC_CONFIG6,
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STNOR_GPMC_CONFIG7
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};
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u32 size = GPMC_SIZE_16M;
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u32 base = CONFIG_SYS_FLASH_BASE;
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#elif defined(CONFIG_NAND)
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/* configure GPMC for NAND */
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const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
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M_NAND_GPMC_CONFIG2,
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M_NAND_GPMC_CONFIG3,
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M_NAND_GPMC_CONFIG4,
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M_NAND_GPMC_CONFIG5,
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M_NAND_GPMC_CONFIG6,
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0
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};
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u32 size = GPMC_SIZE_256M;
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u32 base = CONFIG_SYS_NAND_BASE;
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#elif defined(CONFIG_CMD_ONENAND)
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const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1,
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ONENAND_GPMC_CONFIG2,
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ONENAND_GPMC_CONFIG3,
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ONENAND_GPMC_CONFIG4,
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ONENAND_GPMC_CONFIG5,
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ONENAND_GPMC_CONFIG6,
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0
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};
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u32 base = PISMO1_ONEN_BASE;
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u32 size = PISMO1_ONEN_SIZE;
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#else
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const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
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u32 size = 0;
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u32 base = 0;
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#endif
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/* global settings */
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writel(0x00000008, &gpmc_cfg->sysconfig);
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writel(0x00000000, &gpmc_cfg->irqstatus);
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writel(0x00000000, &gpmc_cfg->irqenable);
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/* disable timeout, set a safe reset value */
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writel(0x00001ff0, &gpmc_cfg->timeout_control);
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#ifdef CONFIG_NOR
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writel(0x00000200, &gpmc_cfg->config);
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#else
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writel(0x00000012, &gpmc_cfg->config);
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#endif
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/*
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* Disable the GPMC0 config set by ROM code
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*/
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writel(0, &gpmc_cfg->cs[0].config7);
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sdelay(1000);
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/* enable chip-select specific configurations */
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if (base != 0)
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enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
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}
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