u-boot-brain/arch
Lokesh Vutla c2562d7c9e arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.

Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
  capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
  C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
  and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
  PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
  up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
  addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
  capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
  16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
  I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
  management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
  capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
  Management (DMSC)

See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1

Add base support for J721E SoC

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-07-26 21:49:25 -04:00
..
arc CONFIG_SPL_SYS_[DI]CACHE_OFF: add 2019-05-18 08:15:35 -04:00
arm arm: K3: j721e: Add basic support for J721E SoC definition 2019-07-26 21:49:25 -04:00
m68k Convert to use fsl_esdhc_imx for i.MX platforms 2019-06-23 14:18:34 +08:00
microblaze spl: fix linker size check off-by-one errors 2019-05-05 08:48:50 -04:00
mips mips: mt76xx: Implement new d-cache fix in last_stage_init() 2019-07-05 17:12:27 +02:00
nds32 CONFIG_SPL_SYS_[DI]CACHE_OFF: add 2019-05-18 08:15:35 -04:00
nios2 .gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore 2018-06-18 14:43:12 -04:00
powerpc km: modify Kconfig file organization for KM boards 2019-07-11 10:58:03 +02:00
riscv efi_loader: use predefined constants in crt0_*_efi.S 2019-07-16 22:17:14 +00:00
sandbox - add rtc driver for stm32mp1 2019-07-23 14:16:21 -04:00
sh sh: r0p7734: Remove the board 2019-06-14 12:42:06 +02:00
x86 x86: Add a forward struct declaration in coreboot_tables.h 2019-07-10 16:52:58 -06:00
xtensa CONFIG_SPL_SYS_[DI]CACHE_OFF: add 2019-05-18 08:15:35 -04:00
.gitignore
Kconfig test: dm: add a test for MDIO MUX DM uclass 2019-07-18 16:37:13 -05:00