mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
505 lines
12 KiB
C
505 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <dm.h>
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#include <hwspinlock.h>
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#include <log.h>
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#include <malloc.h>
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#include <asm/arch/gpio.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <dm/pinctrl.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/libfdt.h>
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#define MAX_PINS_ONE_IP 70
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#define MODE_BITS_MASK 3
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#define OSPEED_MASK 3
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#define PUPD_MASK 3
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#define OTYPE_MSK 1
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#define AFR_MASK 0xF
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struct stm32_pinctrl_priv {
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struct hwspinlock hws;
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int pinctrl_ngpios;
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struct list_head gpio_dev;
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};
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struct stm32_gpio_bank {
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struct udevice *gpio_dev;
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struct list_head list;
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};
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#ifndef CONFIG_SPL_BUILD
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static char pin_name[PINNAME_SIZE];
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#define PINMUX_MODE_COUNT 5
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static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
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"gpio input",
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"gpio output",
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"analog",
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"unknown",
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"alt function",
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};
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static const char * const pinmux_bias[] = {
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[STM32_GPIO_PUPD_NO] = "",
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[STM32_GPIO_PUPD_UP] = "pull-up",
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[STM32_GPIO_PUPD_DOWN] = "pull-down",
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};
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static const char * const pinmux_input[] = {
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[STM32_GPIO_OTYPE_PP] = "push-pull",
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[STM32_GPIO_OTYPE_OD] = "open-drain",
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};
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static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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u32 af;
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u32 alt_shift = (offset % 8) * 4;
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u32 alt_index = offset / 8;
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af = (readl(®s->afr[alt_index]) &
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GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
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return af;
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}
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static int stm32_populate_gpio_dev_list(struct udevice *dev)
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{
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struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
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struct udevice *gpio_dev;
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struct udevice *child;
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struct stm32_gpio_bank *gpio_bank;
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int ret;
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/*
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* parse pin-controller sub-nodes (ie gpio bank nodes) and fill
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* a list with all gpio device reference which belongs to the
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* current pin-controller. This list is used to find pin_name and
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* pin muxing
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*/
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list_for_each_entry(child, &dev->child_head, sibling_node) {
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ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
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&gpio_dev);
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if (ret < 0)
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continue;
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gpio_bank = malloc(sizeof(*gpio_bank));
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if (!gpio_bank) {
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dev_err(dev, "Not enough memory\n");
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return -ENOMEM;
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}
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gpio_bank->gpio_dev = gpio_dev;
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list_add_tail(&gpio_bank->list, &priv->gpio_dev);
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}
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return 0;
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}
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static int stm32_pinctrl_get_pins_count(struct udevice *dev)
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{
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struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
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struct gpio_dev_priv *uc_priv;
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struct stm32_gpio_bank *gpio_bank;
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/*
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* if get_pins_count has already been executed once on this
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* pin-controller, no need to run it again
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*/
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if (priv->pinctrl_ngpios)
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return priv->pinctrl_ngpios;
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if (list_empty(&priv->gpio_dev))
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stm32_populate_gpio_dev_list(dev);
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/*
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* walk through all banks to retrieve the pin-controller
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* pins number
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*/
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list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
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uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
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priv->pinctrl_ngpios += uc_priv->gpio_count;
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}
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return priv->pinctrl_ngpios;
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}
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static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
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unsigned int selector,
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unsigned int *idx)
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{
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struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_bank *gpio_bank;
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struct gpio_dev_priv *uc_priv;
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int pin_count = 0;
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if (list_empty(&priv->gpio_dev))
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stm32_populate_gpio_dev_list(dev);
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/* look up for the bank which owns the requested pin */
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list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
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uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
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if (selector < (pin_count + uc_priv->gpio_count)) {
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/*
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* we found the bank, convert pin selector to
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* gpio bank index
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*/
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*idx = stm32_offset_to_index(gpio_bank->gpio_dev,
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selector - pin_count);
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if (IS_ERR_VALUE(*idx))
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return NULL;
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return gpio_bank->gpio_dev;
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}
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pin_count += uc_priv->gpio_count;
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}
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return NULL;
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}
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static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
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unsigned int selector)
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{
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struct gpio_dev_priv *uc_priv;
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struct udevice *gpio_dev;
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unsigned int gpio_idx;
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/* look up for the bank which owns the requested pin */
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gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
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if (!gpio_dev) {
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snprintf(pin_name, PINNAME_SIZE, "Error");
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} else {
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uc_priv = dev_get_uclass_priv(gpio_dev);
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snprintf(pin_name, PINNAME_SIZE, "%s%d",
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uc_priv->bank_name,
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gpio_idx);
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}
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return pin_name;
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}
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static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
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unsigned int selector,
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char *buf,
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int size)
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{
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struct udevice *gpio_dev;
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struct stm32_gpio_priv *priv;
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const char *label;
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int mode;
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int af_num;
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unsigned int gpio_idx;
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u32 pupd, otype;
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/* look up for the bank which owns the requested pin */
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gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
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if (!gpio_dev)
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return -ENODEV;
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mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
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dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
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selector, gpio_idx, mode);
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priv = dev_get_priv(gpio_dev);
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pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
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switch (mode) {
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case GPIOF_UNKNOWN:
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/* should never happen */
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return -EINVAL;
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case GPIOF_UNUSED:
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snprintf(buf, size, "%s", pinmux_mode[mode]);
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break;
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case GPIOF_FUNC:
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af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
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snprintf(buf, size, "%s %d %s", pinmux_mode[mode], af_num,
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pinmux_bias[pupd]);
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break;
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case GPIOF_OUTPUT:
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snprintf(buf, size, "%s %s %s",
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pinmux_mode[mode], pinmux_bias[pupd],
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label ? label : "");
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break;
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case GPIOF_INPUT:
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otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
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snprintf(buf, size, "%s %s %s %s",
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pinmux_mode[mode], pinmux_input[otype],
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pinmux_bias[pupd], label ? label : "");
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break;
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}
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return 0;
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}
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#endif
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static int stm32_pinctrl_probe(struct udevice *dev)
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{
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struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
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int ret;
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INIT_LIST_HEAD(&priv->gpio_dev);
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/* hwspinlock property is optional, just log the error */
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ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
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if (ret)
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debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
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__func__, ret);
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return 0;
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}
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static int stm32_gpio_config(struct gpio_desc *desc,
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const struct stm32_gpio_ctl *ctl)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
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struct stm32_gpio_regs *regs = priv->regs;
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struct stm32_pinctrl_priv *ctrl_priv;
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int ret;
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u32 index;
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if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
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ctl->pupd > 2 || ctl->speed > 3)
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return -EINVAL;
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ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
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ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
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if (ret == -ETIME) {
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dev_err(desc->dev, "HWSpinlock timeout\n");
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return ret;
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}
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index = (desc->offset & 0x07) * 4;
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clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
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ctl->af << index);
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index = desc->offset * 2;
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clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
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ctl->mode << index);
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clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
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ctl->speed << index);
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clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
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index = desc->offset;
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clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
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hwspinlock_unlock(&ctrl_priv->hws);
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return 0;
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}
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static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
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{
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gpio_dsc->port = (port_pin & 0x1F000) >> 12;
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gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
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debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
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gpio_dsc->pin);
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return 0;
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}
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static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn,
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ofnode node)
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{
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gpio_fn &= 0x00FF;
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gpio_ctl->af = 0;
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switch (gpio_fn) {
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case 0:
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gpio_ctl->mode = STM32_GPIO_MODE_IN;
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break;
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case 1 ... 16:
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gpio_ctl->mode = STM32_GPIO_MODE_AF;
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gpio_ctl->af = gpio_fn - 1;
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break;
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case 17:
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gpio_ctl->mode = STM32_GPIO_MODE_AN;
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break;
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default:
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gpio_ctl->mode = STM32_GPIO_MODE_OUT;
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break;
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}
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gpio_ctl->speed = ofnode_read_u32_default(node, "slew-rate", 0);
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if (ofnode_read_bool(node, "drive-open-drain"))
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gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
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else
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gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
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if (ofnode_read_bool(node, "bias-pull-up"))
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gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
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else if (ofnode_read_bool(node, "bias-pull-down"))
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gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
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else
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gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
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debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
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__func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
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gpio_ctl->pupd);
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return 0;
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}
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static int stm32_pinctrl_config(ofnode node)
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{
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u32 pin_mux[MAX_PINS_ONE_IP];
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int rv, len;
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ofnode subnode;
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/*
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* check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
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* usart1) of pin controller phandle "pinctrl-0"
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* */
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ofnode_for_each_subnode(subnode, node) {
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struct stm32_gpio_dsc gpio_dsc;
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struct stm32_gpio_ctl gpio_ctl;
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int i;
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rv = ofnode_read_size(subnode, "pinmux");
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if (rv < 0)
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return rv;
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len = rv / sizeof(pin_mux[0]);
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debug("%s: no of pinmux entries= %d\n", __func__, len);
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if (len > MAX_PINS_ONE_IP)
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return -EINVAL;
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rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
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if (rv < 0)
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return rv;
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for (i = 0; i < len; i++) {
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struct gpio_desc desc;
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debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
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prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
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prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
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rv = uclass_get_device_by_seq(UCLASS_GPIO,
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gpio_dsc.port,
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&desc.dev);
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if (rv)
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return rv;
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desc.offset = gpio_dsc.pin;
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rv = stm32_gpio_config(&desc, &gpio_ctl);
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debug("%s: rv = %d\n\n", __func__, rv);
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if (rv)
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return rv;
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}
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}
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return 0;
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}
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static int stm32_pinctrl_bind(struct udevice *dev)
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{
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ofnode node;
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const char *name;
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int ret;
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dev_for_each_subnode(node, dev) {
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debug("%s: bind %s\n", __func__, ofnode_get_name(node));
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ofnode_get_property(node, "gpio-controller", &ret);
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if (ret < 0)
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continue;
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/* Get the name of each gpio node */
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name = ofnode_get_name(node);
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if (!name)
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return -EINVAL;
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/* Bind each gpio node */
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ret = device_bind_driver_to_node(dev, "gpio_stm32",
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name, node, NULL);
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if (ret)
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return ret;
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debug("%s: bind %s\n", __func__, name);
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}
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return 0;
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}
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#if CONFIG_IS_ENABLED(PINCTRL_FULL)
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static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
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{
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return stm32_pinctrl_config(dev_ofnode(config));
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}
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#else /* PINCTRL_FULL */
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static int stm32_pinctrl_set_state_simple(struct udevice *dev,
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struct udevice *periph)
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{
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const fdt32_t *list;
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uint32_t phandle;
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ofnode config_node;
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int size, i, ret;
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list = ofnode_get_property(dev_ofnode(periph), "pinctrl-0", &size);
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if (!list)
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return -EINVAL;
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debug("%s: periph->name = %s\n", __func__, periph->name);
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size /= sizeof(*list);
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for (i = 0; i < size; i++) {
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phandle = fdt32_to_cpu(*list++);
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config_node = ofnode_get_by_phandle(phandle);
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if (!ofnode_valid(config_node)) {
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pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
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return -EINVAL;
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}
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ret = stm32_pinctrl_config(config_node);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif /* PINCTRL_FULL */
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static struct pinctrl_ops stm32_pinctrl_ops = {
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#if CONFIG_IS_ENABLED(PINCTRL_FULL)
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.set_state = stm32_pinctrl_set_state,
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#else /* PINCTRL_FULL */
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.set_state_simple = stm32_pinctrl_set_state_simple,
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#endif /* PINCTRL_FULL */
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#ifndef CONFIG_SPL_BUILD
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.get_pin_name = stm32_pinctrl_get_pin_name,
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.get_pins_count = stm32_pinctrl_get_pins_count,
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.get_pin_muxing = stm32_pinctrl_get_pin_muxing,
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#endif
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};
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static const struct udevice_id stm32_pinctrl_ids[] = {
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{ .compatible = "st,stm32f429-pinctrl" },
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{ .compatible = "st,stm32f469-pinctrl" },
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{ .compatible = "st,stm32f746-pinctrl" },
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{ .compatible = "st,stm32f769-pinctrl" },
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{ .compatible = "st,stm32h743-pinctrl" },
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{ .compatible = "st,stm32mp157-pinctrl" },
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{ .compatible = "st,stm32mp157-z-pinctrl" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(pinctrl_stm32) = {
|
|
.name = "pinctrl_stm32",
|
|
.id = UCLASS_PINCTRL,
|
|
.of_match = stm32_pinctrl_ids,
|
|
.ops = &stm32_pinctrl_ops,
|
|
.bind = stm32_pinctrl_bind,
|
|
.probe = stm32_pinctrl_probe,
|
|
.priv_auto = sizeof(struct stm32_pinctrl_priv),
|
|
};
|