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https://github.com/brain-hackers/u-boot-brain
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![Jonathan Liu](/assets/img/avatar_default.png)
Similar to the USB NIC found on OMAP5uEVM, PandaBoard and BeagleBoard-XM
boards, the sunxi SoCs have a NIC onboard without an embedded MAC address.
Just like the omap used on these boards, the sunxi SoCs do have a unique chip
id, in the form of the 128 bit SID register:
http://linux-sunxi.org/SID_Register_Guide
So mimick the BeagleBoard-XM board code (commit 548a64d8
) and use the chip id
to generate a unique fixed MAC address.
We check for the SID not being all 0, since some early A20 batches
shipped without having there SID programmed.
Note we use specific parts of the 128 bits, since some parts indicate the
SoC family / revision, and thus are fixed. The algorithm for this was taken
from the linux-sunxi.org kernels.
Signed-off-by: Jonathan Liu <net147@gmail.com>
[hdegoede@redhat.com: Expanded the commit message with some more info]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
188 lines
4.4 KiB
C
188 lines
4.4 KiB
C
/*
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* (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
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* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Some board init for the Allwinner A10-evb board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#ifdef CONFIG_AXP152_POWER
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#include <axp152.h>
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#endif
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#ifdef CONFIG_AXP209_POWER
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#include <axp209.h>
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#endif
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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#include <asm/io.h>
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#include <net.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* add board specific code here */
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int board_init(void)
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{
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int id_pfr1;
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gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
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asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
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debug("id_pfr1: 0x%08x\n", id_pfr1);
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/* Generic Timer Extension available? */
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if ((id_pfr1 >> 16) & 0xf) {
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debug("Setting CNTFRQ\n");
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/* CNTFRQ == 24 MHz */
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asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
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}
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
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return 0;
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}
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#ifdef CONFIG_GENERIC_MMC
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static void mmc_pinmux_setup(int sdc)
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{
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unsigned int pin;
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switch (sdc) {
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case 0:
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/* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
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for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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break;
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case 1:
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/* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */
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for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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break;
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case 2:
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/* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
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for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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break;
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case 3:
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/* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
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for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
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sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
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sunxi_gpio_set_drv(pin, 2);
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}
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break;
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default:
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printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
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break;
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}
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}
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int board_mmc_init(bd_t *bis)
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{
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mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
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sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
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#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
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mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
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sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
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#endif
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return 0;
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}
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#endif
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void i2c_init_board(void)
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{
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sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
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clock_twi_onoff(0, 1);
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}
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#ifdef CONFIG_SPL_BUILD
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void sunxi_board_init(void)
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{
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int power_failed = 0;
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unsigned long ramsize;
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#ifdef CONFIG_AXP152_POWER
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power_failed = axp152_init();
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power_failed |= axp152_set_dcdc2(1400);
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power_failed |= axp152_set_dcdc3(1500);
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power_failed |= axp152_set_dcdc4(1250);
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power_failed |= axp152_set_ldo2(3000);
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#endif
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#ifdef CONFIG_AXP209_POWER
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power_failed |= axp209_init();
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power_failed |= axp209_set_dcdc2(1400);
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power_failed |= axp209_set_dcdc3(1250);
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power_failed |= axp209_set_ldo2(3000);
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power_failed |= axp209_set_ldo3(2800);
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power_failed |= axp209_set_ldo4(2800);
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#endif
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printf("DRAM:");
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ramsize = sunxi_dram_init();
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printf(" %lu MiB\n", ramsize >> 20);
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if (!ramsize)
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hang();
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/*
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* Only clock up the CPU to full speed if we are reasonably
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* assured it's being powered with suitable core voltage
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*/
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if (!power_failed)
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clock_set_pll1(CONFIG_CLK_FULL_SPEED);
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else
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printf("Failed to set core voltage! Can't set CPU frequency\n");
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}
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#endif
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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if (!getenv("ethaddr")) {
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uint32_t reg_val = readl(SUNXI_SID_BASE);
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if (reg_val) {
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uint8_t mac_addr[6];
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mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
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mac_addr[1] = (reg_val >> 0) & 0xff;
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reg_val = readl(SUNXI_SID_BASE + 0x0c);
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mac_addr[2] = (reg_val >> 24) & 0xff;
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mac_addr[3] = (reg_val >> 16) & 0xff;
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mac_addr[4] = (reg_val >> 8) & 0xff;
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mac_addr[5] = (reg_val >> 0) & 0xff;
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eth_setenv_enetaddr("ethaddr", mac_addr);
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}
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}
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return 0;
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}
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#endif
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