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https://github.com/brain-hackers/u-boot-brain
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94752f60eb
A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to increase and cause the PLL to unlock when the temperature delta from the time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC VCO. Only the protocols using Ring VCOs are impacted. Workaround: For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need to use alternate serdes protocols. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
8 lines
219 B
INI
8 lines
219 B
INI
#PBL preamble and RCW header
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aa55aa55 010e0100
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#serdes protocol 1_27_5_11
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16070019 18101916 00000000 00000000
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04362858 30548c00 ec020000 f5000000
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00000000 ee0000ee 00000000 000307fc
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00000000 00000000 00000000 00000028
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