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https://github.com/brain-hackers/u-boot-brain
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ea1af9f26b
On sun9i, the GTBUS manages transaction priority and bandwidth for multiple read ports when accessing DRAM. The initialisation mirrors the settings from Allwinner's boot0 for now, even though this may not be optimal for all applications (e.g. headless systems might want to give priority to IO modules). Adding a common callout to gtbus_init() from the SPL clock init with a weakly defined implementation in sunxi/clock.c to fallback to for platforms that don't require this. [wens@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
/*
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* GTBUS initialisation for sun9i
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*
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* (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
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* Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/gtbus_sun9i.h>
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#include <asm/arch/sys_proto.h>
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#ifdef CONFIG_SPL_BUILD
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void gtbus_init(void)
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{
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struct sunxi_gtbus_reg * const gtbus =
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(struct sunxi_gtbus_reg *)SUNXI_GTBUS_BASE;
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/*
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* We use the same setting that Allwinner used in Boot0 for now.
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* It may be advantageous to adjust these for various workloads
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* (e.g. headless use cases that focus on IO throughput).
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*/
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writel((GT_PRIO_HIGH << GT_PORT_FE0) |
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(GT_PRIO_HIGH << GT_PORT_BE1) |
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(GT_PRIO_HIGH << GT_PORT_BE2) |
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(GT_PRIO_HIGH << GT_PORT_IEP0) |
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(GT_PRIO_HIGH << GT_PORT_FE1) |
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(GT_PRIO_HIGH << GT_PORT_BE0) |
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(GT_PRIO_HIGH << GT_PORT_FE2) |
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(GT_PRIO_HIGH << GT_PORT_IEP1),
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>bus->mst_read_prio_cfg[0]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE0]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE0]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE1]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE2]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_IEP0]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE1]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_BE0]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_FE2]);
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writel(GP_MST_CFG_DEFAULT, >bus->mst_cfg[GT_PORT_IEP1]);
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}
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#endif
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