mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-08 13:53:21 +09:00
f8cf3d1ebd
Some cache operations ({i|d}cache_{enable|disable|status} or
flush_dcache_all) are built and used even if CONFIG_SYS_{I|D}CACHE_OFF
is set.
This is required for force disable of caches on early boot.
What if something was executed before U-boot and enabled caches
(low-level bootloaders, previously run kernel etc.)?
But if CPU doesn't really have caches any attempt to access
cache-related AUX registers triggers instruction error exception.
So for convenience we'll try to avoid exceptions by checking if CPU
actually has caches (we check separately data and instruction cache
existence) at all.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
168 lines
4.1 KiB
C
168 lines
4.1 KiB
C
/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <asm/arcregs.h>
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/* Bit values in IC_CTRL */
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#define IC_CTRL_CACHE_DISABLE (1 << 0)
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/* Bit values in DC_CTRL */
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#define DC_CTRL_CACHE_DISABLE (1 << 0)
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#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
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#define DC_CTRL_FLUSH_STATUS (1 << 8)
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#define CACHE_VER_NUM_MASK 0xF
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int icache_status(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
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return 0;
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return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
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IC_CTRL_CACHE_DISABLE;
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}
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void icache_enable(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
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~IC_CTRL_CACHE_DISABLE);
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}
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void icache_disable(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
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IC_CTRL_CACHE_DISABLE);
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}
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void invalidate_icache_all(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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/* Any write to IC_IVIC register triggers invalidation of entire I$ */
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write_aux_reg(ARC_AUX_IC_IVIC, 1);
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#endif /* CONFIG_SYS_ICACHE_OFF */
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}
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int dcache_status(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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return 0;
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return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
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DC_CTRL_CACHE_DISABLE;
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}
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void dcache_enable(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
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~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
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}
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void dcache_disable(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
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DC_CTRL_CACHE_DISABLE);
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}
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void flush_dcache_all(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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/* Do flush of entire cache */
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write_aux_reg(ARC_AUX_DC_FLSH, 1);
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/* Wait flush end */
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while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
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;
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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static void dcache_flush_line(unsigned addr)
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{
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#if (CONFIG_ARC_MMU_VER > 2)
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write_aux_reg(ARC_AUX_DC_PTAG, addr);
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#endif
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write_aux_reg(ARC_AUX_DC_FLDL, addr);
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/* Wait flush end */
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while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
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;
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#ifndef CONFIG_SYS_ICACHE_OFF
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/*
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* Invalidate I$ for addresses range just flushed from D$.
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* If we try to execute data flushed above it will be valid/correct
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*/
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#if (CONFIG_ARC_MMU_VER > 2)
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write_aux_reg(ARC_AUX_IC_PTAG, addr);
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#endif
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write_aux_reg(ARC_AUX_IC_IVIL, addr);
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#endif /* CONFIG_SYS_ICACHE_OFF */
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}
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#endif /* CONFIG_SYS_DCACHE_OFF */
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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unsigned int addr;
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start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
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end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
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for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
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dcache_flush_line(addr);
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#endif /* CONFIG_SYS_DCACHE_OFF */
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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unsigned int addr;
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start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
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end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
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for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
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#if (CONFIG_ARC_MMU_VER > 2)
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write_aux_reg(ARC_AUX_DC_PTAG, addr);
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#endif
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write_aux_reg(ARC_AUX_DC_IVDL, addr);
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}
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#endif /* CONFIG_SYS_DCACHE_OFF */
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}
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void invalidate_dcache_all(void)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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/* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
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write_aux_reg(ARC_AUX_DC_IVDC, 1);
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#endif /* CONFIG_SYS_DCACHE_OFF */
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}
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void flush_cache(unsigned long start, unsigned long size)
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{
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flush_dcache_range(start, start + size);
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}
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