Masahiro Yamada c72f4d4c2e ARM: uniphier: add PLL init code for LD11 SoC ... - Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>		2016-09-23 01:00:23 +09:00
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init-ld4.c	ARM: uniphier: move PLL init code to U-Boot proper where possible	2016-09-19 00:06:44 +09:00
init-ld11.c	ARM: uniphier: add PLL init code for LD11 SoC	2016-09-23 01:00:23 +09:00
init-ld20.c	ARM: uniphier: add PLL init code for LD20 SoC	2016-09-19 00:12:26 +09:00
init-pro4.c	ARM: uniphier: move PLL init code to U-Boot proper where possible	2016-09-19 00:06:44 +09:00
init-pro5.c	ARM: uniphier: rename function names ph1_* to uniphier_*	2016-04-01 00:59:47 +09:00
init-pxs2.c	ARM: uniphier: rename function names ph1_* to uniphier_*	2016-04-01 00:59:47 +09:00
init-sld3.c	ARM: uniphier: move PLL init code to U-Boot proper where possible	2016-09-19 00:06:44 +09:00
init-sld8.c	ARM: uniphier: move PLL init code to U-Boot proper where possible	2016-09-19 00:06:44 +09:00
init.c	ARM: uniphier: add PH1-LD11 SoC support	2016-05-26 00:37:13 +09:00
Makefile	ARM: uniphier: add PH1-LD11 SoC support	2016-05-26 00:37:13 +09:00