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https://github.com/brain-hackers/u-boot-brain
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314 lines
9.0 KiB
C
314 lines
9.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale MX28EVK board
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*
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* (C) Copyright 2011 Freescale Semiconductor, Inc.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* Based on m28evk.c:
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/mii.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Functions
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*/
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int board_early_init_f(void)
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{
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/* IO0 clock at 480MHz */
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mxs_set_ioclk(MXC_IOCLK0, 480000);
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/* IO1 clock at 480MHz */
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mxs_set_ioclk(MXC_IOCLK1, 480000);
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/* SSP0 clock at 96MHz */
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mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
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/* SSP1 clock at 96MHz */
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mxs_set_sspclk(MXC_SSPCLK1, 96000, 0);
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#ifdef CONFIG_CMD_USB
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mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
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mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
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MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
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gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = 0x8000000; // 128MiB
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return 0;
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}
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int board_init(void)
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{
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/* Adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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#ifdef CONFIG_CMD_MMC
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static int mx28evk_mmc_wp(int id)
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{
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return 0;
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}
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static int mx28evk_mmc_cd(int id)
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{
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return 1;
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}
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int board_mmc_init(bd_t *bis)
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{
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mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, mx28evk_mmc_cd);
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mxsmmc_initialize(bis, 1, mx28evk_mmc_wp, mx28evk_mmc_cd);
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/* Turn on the SD*/
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gpio_direction_output(MX28_PAD_SSP2_SS2__GPIO_2_21, 0);
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return 0;
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}
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#endif
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct eth_device *dev;
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int ret;
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ret = cpu_eth_init(bis);
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if (ret)
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return ret;
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/* MX28EVK uses ENET_CLK PAD to drive FEC clock */
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writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
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&clkctrl_regs->hw_clkctrl_enet);
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/* Power-on FECs */
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gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
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/* Reset FEC PHYs */
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gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
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udelay(200);
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gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
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ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
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if (ret) {
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puts("FEC MXS: Unable to init FEC0\n");
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return ret;
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}
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ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
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if (ret) {
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puts("FEC MXS: Unable to init FEC1\n");
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return ret;
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}
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dev = eth_get_dev_by_name("FEC0");
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if (!dev) {
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puts("FEC MXS: Unable to get FEC0 device entry\n");
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return -EINVAL;
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}
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dev = eth_get_dev_by_name("FEC1");
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if (!dev) {
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puts("FEC MXS: Unable to get FEC1 device entry\n");
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return -EINVAL;
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}
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return ret;
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}
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#endif
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#ifdef CONFIG_VIDEO_MXS
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static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
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{
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struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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const unsigned int timeout = 0x10000;
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if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, timeout))
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return -ETIMEDOUT;
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writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
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(1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
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®s->hw_lcdif_transfer_count);
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writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
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®s->hw_lcdif_ctrl_clr);
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if (data)
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writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set);
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writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
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if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29,
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timeout))
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return -ETIMEDOUT;
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writel(payload, ®s->hw_lcdif_data);
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return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
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timeout);
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}
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/* https://github.com/muojie/spec_mtk/blob/master/MTK_driver/spec/LCM/ILI9805/ILI9805_AN_V0.4_20120330.pdf */
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static const struct {
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uint32_t payload;
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unsigned int data;
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uint32_t delay;
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} lcd_regs[] = {
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{ 0xff, 0, 0 }, /* EXTC Command Set Enable */
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{ 0xff, 1, 0 }, { 0x98, 1, 0 }, { 0x05, 1, 0 },
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{ 0xfd, 0, 0 }, /* PFM Type C */
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{ 0x03, 1, 0 }, { 0x13, 1, 0 }, { 0x44, 1, 0 }, { 0x00, 1, 0 },
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{ 0xf8, 0, 0 }, /* PFM Type C */
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{ 0x18, 1, 0 }, { 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x18, 1, 0 },
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{ 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 },
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{ 0x01, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
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{ 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
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{ 0xb8, 0, 0 }, /* DBI Type B Interface Setting */
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{ 0x72, 1, 0 },
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{ 0xf1, 0, 0 }, /* Gate Modulation */
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{ 0x00, 1, 0 },
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{ 0xf2, 0, 0 }, /* CR/EQ/PC */
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{ 0x00, 1, 0 }, { 0x58, 1, 0 }, { 0x40, 1, 0 },
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{ 0xfc, 0, 0 }, /* LVGL Voltage Setting? */
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{ 0x04, 1, 0 }, { 0x0f, 1, 0 }, { 0x01, 1, 0 },
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{ 0xeb, 0, 0 }, /* ? */
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{ 0x08, 1, 0 }, { 0x0f, 1, 0 },
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{ 0xe0, 0, 0 }, /* Positive Gamma Control */
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{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x35, 1, 0 }, { 0x15, 1, 0 },
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{ 0x13, 1, 0 }, { 0x16, 1, 0 }, { 0x0a, 1, 0 }, { 0x06, 1, 0 },
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{ 0x03, 1, 0 }, { 0x06, 1, 0 }, { 0x05, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x08, 1, 0 }, { 0x23, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
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{ 0xe1, 0, 0 }, /* Negative Gamma Control */
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{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x28, 1, 0 }, { 0x10, 1, 0 },
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{ 0x11, 1, 0 }, { 0x16, 1, 0 }, { 0x0b, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x02, 1, 0 }, { 0x05, 1, 0 }, { 0x04, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x08, 1, 0 }, { 0x1d, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
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{ 0xc1, 0, 0 }, /* Power Control 1 */
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{ 0x13, 1, 0 }, { 0x28, 1, 0 }, { 0x08, 1, 0 }, { 0x26, 1, 0 },
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{ 0xc7, 0, 0 }, /* VCOM Control */
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{ 0x90, 1, 0 },
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{ 0xb1, 0, 0 }, /* Frame Rate Control */
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{ 0x00, 1, 0 }, { 0x12, 1, 0 }, { 0x14, 1, 0 },
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{ 0xb4, 0, 0 }, /* Display Inversion Control */
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{ 0x02, 1, 0 },
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{ 0xbb, 0, 0 }, /* ? */
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{ 0x14, 1, 0 }, { 0x55, 1, 0 },
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{ 0x36, 0, 0 }, /* Memory Access Control */
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{ 0x28, 1, 0 },
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{ 0x3a, 0, 0 }, /* Interface Pixel Format */
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{ 0x55, 1, 0 },
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{ 0x21, 0, 0 }, /* Display Inversion On */
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{ 0xb6, 0, 0 }, /* MCU/RGB Interface Select */
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{ 0x01, 1, 0 }, { 0x80, 1, 0 }, { 0x8f, 1, 0 },
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{ 0x44, 0, 0 }, /* Write Tear Scan Line? */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 },
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{ 0x35, 0, 0 }, /* Tearing Effect Line On */
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{ 0x00, 1, 0 },
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{ 0x11, 0, 120 }, /* Sleep Out */
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{ 0x29, 0, 20 }, /* Display On */
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{ 0x2a, 0, 0 }, /* Column Address Set */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x03, 1, 0 }, { 0x1f, 1, 0 },
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{ 0x2b, 0, 0 }, /* Page Address Set */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x01, 1, 0 }, { 0xdf, 1, 0 },
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{ 0x2c, 0, 0 }, /* Memory Write*/
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};
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void mxsfb_system_setup(void)
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{
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struct mxs_lcdif_regs *lcdif = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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struct mxs_clkctrl_regs *xtal = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct mxs_pwm_regs *pwm = (struct mxs_pwm_regs *)MXS_PWM_BASE;
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int i, j;
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uint32_t valid_data;
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valid_data = readl(&lcdif->hw_lcdif_ctrl1) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK;
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writel(0x3 << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
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&lcdif->hw_lcdif_ctrl1);
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/* Switch the LCDIF into System-Mode */
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writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
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LCDIF_CTRL_BYPASS_COUNT, &lcdif->hw_lcdif_ctrl_clr);
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writel(LCDIF_CTRL_VSYNC_MODE, &lcdif->hw_lcdif_ctrl_set);
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writel(LCDIF_VDCTRL3_VSYNC_ONLY, &lcdif->hw_lcdif_vdctrl3_set);
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writel((0x01 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
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(0x01 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
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(0x01 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
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(0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET),
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&lcdif->hw_lcdif_timing);
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/* Enable LCD Controller */
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gpio_direction_output(MX28_PAD_GPMI_ALE__GPIO_0_26, 1);
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gpio_direction_output(MX28_PAD_GPMI_CLE__GPIO_0_27, 1);
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gpio_direction_output(MX28_PAD_ENET_CLK__GPIO_4_16, 1);
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mdelay(20);
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for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
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mxsfb_write_byte(lcd_regs[i].payload, lcd_regs[i].data);
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if (lcd_regs[i].delay)
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mdelay(lcd_regs[i].delay);
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}
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/* Fill black */
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for (i = 0; i < 480; i++) {
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for (j = 0; j < 800; j++) {
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mxsfb_write_byte(0, 1);
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}
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}
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writel(valid_data, &lcdif->hw_lcdif_ctrl1);
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writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
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&lcdif->hw_lcdif_ctrl_set);
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/* Turn on backlight */
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writel(CLKCTRL_XTAL_PWM_CLK24M_GATE, &xtal->hw_clkctrl_xtal_clr);
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mdelay(1);
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writel(PWM_CTRL_SFTRST, &pwm->hw_pwm_ctrl_clr);
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writel(PWM_CTRL_CLKGATE, &pwm->hw_pwm_ctrl_clr);
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writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE, &pwm->hw_pwm_ctrl_clr);
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writel((0x005a << PWM_ACTIVE0_INACTIVE_OFFSET) |
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(0x0000 << PWM_ACTIVE0_ACTIVE_OFFSET), &pwm->hw_pwm_active0_set);
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writel((0x00f0 << PWM_ACTIVE1_INACTIVE_OFFSET) |
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(0x0000 << PWM_ACTIVE1_ACTIVE_OFFSET), &pwm->hw_pwm_active1_set);
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writel((0x1 << PWM_PERIOD0_CDIV_OFFSET) |
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(0x2 << PWM_PERIOD0_INACTIVE_STATE_OFFSET) |
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(0x3 << PWM_PERIOD0_ACTIVE_STATE_OFFSET) |
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(0x01f3 << PWM_PERIOD0_PERIOD_OFFSET), &pwm->hw_pwm_period0_set);
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writel((0x0 << PWM_PERIOD1_CDIV_OFFSET) |
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(0x3 << PWM_PERIOD1_INACTIVE_STATE_OFFSET) |
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(0x3 << PWM_PERIOD1_ACTIVE_STATE_OFFSET) |
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(0x07cf << PWM_PERIOD1_PERIOD_OFFSET), &pwm->hw_pwm_period1_set);
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writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE, &pwm->hw_pwm_ctrl_set);
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}
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#endif
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