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https://github.com/brain-hackers/u-boot-brain
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c7190f028f
some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> |
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| .. | ||
| config.mk | ||
| cpu_init.c | ||
| cpu.c | ||
| ecc.c | ||
| fdt.c | ||
| interrupts.c | ||
| Makefile | ||
| nand_init.c | ||
| pci.c | ||
| pcie.c | ||
| qe_io.c | ||
| serdes.c | ||
| spd_sdram.c | ||
| speed.c | ||
| start.S | ||
| traps.c | ||
| u-boot.lds | ||