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https://github.com/brain-hackers/u-boot-brain
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![Heiko Schocher](/assets/img/avatar_default.png)
u-boot updates, before starting Linux, the memory node in the DTS. As this is a "standard" feature, move this functionality to the cpu.c file for mpc5xxx and mpc512x processors. Signed-off-by: Heiko Schocher <hs@denx.de>
278 lines
7.3 KiB
C
278 lines
7.3 KiB
C
/*
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* (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
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* (C) Copyright 2009 Dave Srl www.dave.eu
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* (C) Copyright 2009 Stefan Roese <sr@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/bitops.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/mpc512x.h>
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#include <fdt_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_NFC_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_I2C_EN)
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int eeprom_write_enable(unsigned dev_addr, int state)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
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return -1;
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if (state == 0)
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setbits_be32(&im->gpio.gpdat, 0x00100000);
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else
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clrbits_be32(&im->gpio.gpdat, 0x00100000);
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return 0;
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}
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int board_early_init_f(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 spridr;
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int i;
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/*
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* Initialize Local Window for NOR FLASH access
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*/
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out_be32(&im->sysconf.lpcs0aw,
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CSAW_START(CONFIG_SYS_FLASH_BASE) |
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CSAW_STOP(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
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sync_law(&im->sysconf.lpcs0aw);
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/*
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* Initialize Local Window for boot access
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*/
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out_be32(&im->sysconf.lpbaw,
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CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
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sync_law(&im->sysconf.lpbaw);
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/*
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* Initialize Local Window for VPC3 access
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*/
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out_be32(&im->sysconf.lpcs1aw,
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CSAW_START(CONFIG_SYS_VPC3_BASE) |
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CSAW_STOP(CONFIG_SYS_VPC3_BASE, CONFIG_SYS_VPC3_SIZE));
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sync_law(&im->sysconf.lpcs1aw);
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/*
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* Configure Flash Speed
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*/
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out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
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/*
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* Configure VPC3 Speed
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*/
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out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
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spridr = in_be32(&im->sysconf.spridr);
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if (SVR_MJREV(spridr) >= 2)
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out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
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/*
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* Enable clocks
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*/
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out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
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out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
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#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
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setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
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#endif
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/*
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* Configure MSCAN clocks
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*/
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for (i=0; i<4; ++i) {
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out_be32(&im->clk.msccr[i], 0x00300000);
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out_be32(&im->clk.msccr[i], 0x00310000);
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}
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/*
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* Configure GPIO's
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*/
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clrbits_be32(&im->gpio.gpodr, 0x000000e0);
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clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
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setbits_be32(&im->gpio.gpdir, 0x001000e0);
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setbits_be32(&im->gpio.gpdat, 0x00100000);
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
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}
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int misc_init_r(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 val;
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/*
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* Optimize access to profibus chip (VPC3) on the local bus
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*/
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/*
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* Select 1:1 for LPC_DIV
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*/
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val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
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out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
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/*
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* Configure LPC Chips Select Deadcycle Control Register
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* CS0 - device can drive data 2 clock cycle(s) after CS deassertion
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* CS1 - device can drive data 1 clock cycle(s) after CS deassertion
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*/
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clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
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setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
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/*
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* Configure LPC Chips Select Holdcycle Control Register
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* CS0 - data is valid 2 clock cycle(s) after CS deassertion
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* CS1 - data is valid 1 clock cycle(s) after CS deassertion
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*/
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clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
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setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
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return 0;
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}
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static iopin_t ioregs_init[] = {
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/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
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{
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offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
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{
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offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC1=SELECT LPC_CS1 */
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{
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offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
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IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC3=SELECT PSC5_2 */
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{
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offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC3=SELECT PSC5_3 */
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{
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offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC3=SELECT PSC7_3 */
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{
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offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC3=SELECT PSC9_0 */
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{
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offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC3=SELECT PSC10_0 */
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{
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offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC3=SELECT PSC10_3 */
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{
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offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
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IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC3=SELECT PSC11_0 */
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{
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offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
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IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC0=SELECT IRQ0 */
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{
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offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
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IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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}
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};
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static iopin_t rev2_silicon_pci_ioregs_init[] = {
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/* FUNC0=PCI Sets next 54 to PCI pads */
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{
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offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
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IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
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}
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};
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int checkboard(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 spridr;
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puts("Board: MECP_5123\n");
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/*
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* Initialize function mux & slew rate IO inter alia on IO
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* Pins
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*/
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iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
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spridr = in_be32(&im->sysconf.spridr);
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if (SVR_MJREV(spridr) >= 2)
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iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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