mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
d5abcf94c7
To keep a consistent MMC device mapping in SPL and in u-boot, let's register the MMC controllers the same way in u-boot and in the SPL. In terms of boot time, it doesn't hurt to register more controllers than needed because the MMC device is initialized only prior being accessed for the first time. Having the same device mapping in SPL and u-boot allows us to use the environment in SPL whatever the MMC boot device. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
112 lines
2.5 KiB
C
112 lines
2.5 KiB
C
/*
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* Copyright (c) 2014 DENX
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* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
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*
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* Derived from code written by Robert Aigner (ra@spiid.net)
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*
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* Itself derived from Beagle Board and 3430 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <netdev.h>
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#include <ns16550.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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#include <asm/mach-types.h>
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#include <asm/omap_mmc.h>
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#include "cairo.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
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*/
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u8 omap3_evm_need_extvbus(void)
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{
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u8 retval = 0;
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/* TODO: verify if cairo handheld platform needs extvbus programming */
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return retval;
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}
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* board id for Linux */
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gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_CAIRO();
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}
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#if defined(CONFIG_GENERIC_MMC)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on the first bank. This
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* provides the timing values back to the function that configures
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* the memory.
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*
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* The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
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*/
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void get_board_mem_timings(struct board_sdrc_timings *timings)
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{
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timings->sharing = SAMSUNG_SHARING;
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timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
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timings->ctrla = SAMSUNG_V_ACTIMA_165;
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timings->ctrlb = SAMSUNG_V_ACTIMB_165;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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timings->mr = SAMSUNG_V_MR_165;
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}
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#endif
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static const struct ns16550_platdata cairo_serial = {
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.base = OMAP34XX_UART2,
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.reg_shift = 2,
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.clock = V_NS16550_CLK,
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.fcr = UART_FCR_DEFVAL,
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};
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U_BOOT_DEVICE(cairo_uart) = {
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"ns16550_serial",
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&cairo_serial
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};
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/* force SPL booting into U-Boot, not Linux */
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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return 1;
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}
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#endif
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