mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-30 05:48:51 +09:00
c02a4242c8
SDRAM init needs access to the Northbridge controller and the Intel Management Engine device. Add the latter to the device tree and convert all of this code to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
312 lines
6.7 KiB
Plaintext
312 lines
6.7 KiB
Plaintext
/dts-v1/;
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/include/ "skeleton.dtsi"
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/include/ "keyboard.dtsi"
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/include/ "serial.dtsi"
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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/ {
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model = "Google Link";
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compatible = "google,link", "intel,celeron-ivybridge";
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aliases {
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spi0 = "/pci/pch/spi";
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};
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config {
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silent_console = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,core-gen3";
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reg = <0>;
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intel,apic-id = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "intel,core-gen3";
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reg = <1>;
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intel,apic-id = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "intel,core-gen3";
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reg = <2>;
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intel,apic-id = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "intel,core-gen3";
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reg = <3>;
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intel,apic-id = <3>;
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};
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0 0x10>;
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bank-name = "A";
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x30 0x10>;
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bank-name = "B";
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};
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gpioc {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x40 0x10>;
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bank-name = "C";
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};
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chosen {
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stdout-path = "/serial";
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};
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keyboard {
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intel,duplicate-por;
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};
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spd {
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compatible = "memory-spd";
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#address-cells = <1>;
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#size-cells = <0>;
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elpida_4Gb_1600_x16 {
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reg = <0>;
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data = [92 10 0b 03 04 19 02 02
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03 52 01 08 0a 00 fe 00
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69 78 69 3c 69 11 18 81
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20 08 3c 3c 01 40 83 81
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 0f 11 42 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 02 fe 00
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11 52 00 00 00 07 7f 37
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45 42 4a 32 30 55 47 36
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45 42 55 30 2d 47 4e 2d
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46 20 30 20 02 fe 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00];
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};
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samsung_4Gb_1600_1.35v_x16 {
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reg = <1>;
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data = [92 11 0b 03 04 19 02 02
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03 11 01 08 0a 00 fe 00
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69 78 69 3c 69 11 18 81
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f0 0a 3c 3c 01 40 83 01
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00 80 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 0f 11 02 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 80 ce 01
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00 00 00 00 00 00 6a 04
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4d 34 37 31 42 35 36 37
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34 42 48 30 2d 59 4b 30
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20 20 00 00 80 ce 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00];
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};
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micron_4Gb_1600_1.35v_x16 {
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reg = <2>;
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data = [92 11 0b 03 04 19 02 02
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03 11 01 08 0a 00 fe 00
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69 78 69 3c 69 11 18 81
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20 08 3c 3c 01 40 83 05
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 0f 01 02 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 80 2c 00
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00 00 00 00 00 00 ad 75
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34 4b 54 46 32 35 36 36
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34 48 5a 2d 31 47 36 45
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31 20 45 31 80 2c 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff];
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};
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};
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pci {
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compatible = "pci-x86";
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#address-cells = <3>;
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#size-cells = <2>;
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u-boot,dm-pre-reloc;
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ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
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0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
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0x01000000 0x0 0x1000 0x1000 0 0xefff>;
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northbridge@0,0 {
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reg = <0x00000000 0 0 0 0>;
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compatible = "intel,bd82x6x-northbridge";
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u-boot,dm-pre-reloc;
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};
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gma {
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compatible = "intel,gma";
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intel,dp_hotplug = <0 0 0x06>;
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intel,panel-port-select = <1>;
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intel,panel-power-cycle-delay = <6>;
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intel,panel-power-up-delay = <2000>;
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intel,panel-power-down-delay = <500>;
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intel,panel-power-backlight-on-delay = <2000>;
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intel,panel-power-backlight-off-delay = <2000>;
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intel,cpu-backlight = <0x00000200>;
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intel,pch-backlight = <0x04000000>;
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};
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me@16,0 {
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reg = <0x0000b000 0 0 0 0>;
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compatible = "intel,me";
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u-boot,dm-pre-reloc;
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};
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pch@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "intel,bd82x6x", "intel,pch9";
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
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0x80 0x80 0x80 0x80>;
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intel,gpi-routing = <0 0 0 0 0 0 0 2
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1 0 0 0 0 0 0 0>;
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/* Enable EC SMI source */
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intel,alt-gp-smi-enable = <0x0100>;
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich-spi";
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spi-flash@0 {
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#size-cells = <1>;
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#address-cells = <1>;
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reg = <0>;
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compatible = "winbond,w25q64",
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"spi-flash";
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memory-map = <0xff800000 0x00800000>;
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rw-mrc-cache {
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label = "rw-mrc-cache";
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reg = <0x003e0000 0x00010000>;
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};
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};
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};
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lpc {
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compatible = "intel,bd82x6x-lpc";
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#address-cells = <1>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
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cros-ec@200 {
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compatible = "google,cros-ec";
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reg = <0x204 1 0x200 1 0x880 0x80>;
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/*
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* Describes the flash memory within
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* the EC
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*/
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#address-cells = <1>;
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#size-cells = <1>;
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flash@8000000 {
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reg = <0x08000000 0x20000>;
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erase-value = <0xff>;
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};
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};
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};
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};
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sata@1f,2 {
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compatible = "intel,pantherpoint-ahci";
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reg = <0x0000fa00 0 0 0 0>;
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u-boot,dm-pre-reloc;
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intel,sata-mode = "ahci";
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intel,sata-port-map = <1>;
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intel,sata-port0-gen3-tx = <0x00880a7f>;
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};
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smbus: smbus@1f,3 {
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compatible = "intel,ich-i2c";
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reg = <0x0000fb00 0 0 0 0>;
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u-boot,dm-pre-reloc;
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};
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};
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tpm {
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reg = <0xfed40000 0x5000>;
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compatible = "infineon,slb9635lpc";
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};
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microcode {
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update@0 {
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#include "microcode/m12306a9_0000001b.dtsi"
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};
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};
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};
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