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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
SDRAM init needs access to the Northbridge controller and the Intel Management Engine device. Add the latter to the device tree and convert all of this code to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
201 lines
4.3 KiB
C
201 lines
4.3 KiB
C
/*
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* From Coreboot src/southbridge/intel/bd82x6x/early_me.c
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*
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* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/pci.h>
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#include <asm/processor.h>
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#include <asm/arch/me.h>
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#include <asm/arch/pch.h>
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#include <asm/io.h>
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static const char *const me_ack_values[] = {
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[ME_HFS_ACK_NO_DID] = "No DID Ack received",
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[ME_HFS_ACK_RESET] = "Non-power cycle reset",
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[ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
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[ME_HFS_ACK_S3] = "Go to S3",
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[ME_HFS_ACK_S4] = "Go to S4",
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[ME_HFS_ACK_S5] = "Go to S5",
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[ME_HFS_ACK_GBL_RESET] = "Global Reset",
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[ME_HFS_ACK_CONTINUE] = "Continue to boot"
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};
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static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
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int offset)
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{
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u32 dword;
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dm_pci_read_config32(me_dev, offset, &dword);
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memcpy(ptr, &dword, sizeof(dword));
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}
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static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
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int offset)
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{
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u32 dword = 0;
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memcpy(&dword, ptr, sizeof(dword));
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dm_pci_write_config32(me_dev, offset, dword);
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}
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void intel_early_me_status(struct udevice *me_dev)
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{
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struct me_hfs hfs;
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struct me_gmes gmes;
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pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
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pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES);
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intel_me_status(&hfs, &gmes);
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}
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int intel_early_me_init(struct udevice *me_dev)
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{
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int count;
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struct me_uma uma;
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struct me_hfs hfs;
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debug("Intel ME early init\n");
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/* Wait for ME UMA SIZE VALID bit to be set */
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for (count = ME_RETRY; count > 0; --count) {
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pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
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if (uma.valid)
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break;
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udelay(ME_DELAY);
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}
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if (!count) {
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printf("ERROR: ME is not ready!\n");
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return -EBUSY;
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}
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/* Check for valid firmware */
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pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
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if (hfs.fpt_bad) {
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printf("WARNING: ME has bad firmware\n");
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return -EBADF;
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}
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debug("Intel ME firmware is ready\n");
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return 0;
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}
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int intel_early_me_uma_size(struct udevice *me_dev)
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{
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struct me_uma uma;
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pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
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if (uma.valid) {
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debug("ME: Requested %uMB UMA\n", uma.size);
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return uma.size;
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}
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debug("ME: Invalid UMA size\n");
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return -EINVAL;
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}
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static inline void set_global_reset(struct udevice *dev, int enable)
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{
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u32 etr3;
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dm_pci_read_config32(dev, ETR3, &etr3);
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/* Clear CF9 Without Resume Well Reset Enable */
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etr3 &= ~ETR3_CWORWRE;
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/* CF9GR indicates a Global Reset */
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if (enable)
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etr3 |= ETR3_CF9GR;
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else
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etr3 &= ~ETR3_CF9GR;
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dm_pci_write_config32(dev, ETR3, etr3);
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}
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int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
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uint status)
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{
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int count;
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u32 mebase_l, mebase_h;
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struct me_hfs hfs;
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struct me_did did = {
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.init_done = ME_INIT_DONE,
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.status = status
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};
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/* MEBASE from MESEG_BASE[35:20] */
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dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L, &mebase_l);
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dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H, &mebase_h);
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mebase_h &= 0xf;
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did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
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/* Send message to ME */
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debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n",
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status, did.uma_base);
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pci_write_dword_ptr(me_dev, &did, PCI_ME_H_GS);
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/* Must wait for ME acknowledgement */
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for (count = ME_RETRY; count > 0; --count) {
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pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
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if (hfs.bios_msg_ack)
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break;
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udelay(ME_DELAY);
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}
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if (!count) {
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printf("ERROR: ME failed to respond\n");
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return -ETIMEDOUT;
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}
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/* Return the requested BIOS action */
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debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
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/* Check status after acknowledgement */
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intel_early_me_status(me_dev);
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switch (hfs.ack_data) {
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case ME_HFS_ACK_CONTINUE:
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/* Continue to boot */
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return 0;
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case ME_HFS_ACK_RESET:
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/* Non-power cycle reset */
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set_global_reset(dev, 0);
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reset_cpu(0);
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break;
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case ME_HFS_ACK_PWR_CYCLE:
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/* Power cycle reset */
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set_global_reset(dev, 0);
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x86_full_reset();
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break;
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case ME_HFS_ACK_GBL_RESET:
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/* Global reset */
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set_global_reset(dev, 1);
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x86_full_reset();
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break;
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case ME_HFS_ACK_S3:
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case ME_HFS_ACK_S4:
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case ME_HFS_ACK_S5:
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break;
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}
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return -EINVAL;
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}
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static const struct udevice_id ivybridge_syscon_ids[] = {
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{ .compatible = "intel,me", },
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{ }
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};
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U_BOOT_DRIVER(syscon_intel_me) = {
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.name = "intel_me_syscon",
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.id = UCLASS_SYSCON,
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.of_match = ivybridge_syscon_ids,
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};
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