mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
d98b0523cf
Now that warm booting is not supported, there isn't a need for the BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them. Note that this change makes the board info bd_bootflags field useless. It will always be set to 0, but we leave it around so that we don't break the board info structure that some OSes are expecting to be passed from U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
273 lines
9.7 KiB
C
273 lines
9.7 KiB
C
/*
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* (C) Copyright 2003
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* Martin Winistoerfer, martinwinistoerfer@gmx.ch.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation,
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*/
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/*
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* File: cmi_mpc5xx.h
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*
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* Discription: Config header file for cmi
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* board using an MPC5xx CPU
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
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#define CONFIG_CMI 1 /* Using the customized cmi board */
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#define CONFIG_SYS_TEXT_BASE 0x02000000 /* Boot from flash at location 0x00000000 */
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/* Serial Console Configuration */
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#define CONFIG_5xx_CONS_SCI1
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#undef CONFIG_5xx_CONS_SCI2
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#define CONFIG_BAUDRATE 57600
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_NET /* disabeled - causes compile errors */
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_CONSOLE
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_IMI
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */
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#define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */
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#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
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#define CONFIG_STATUS_LED 1 /* Enable status led */
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#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x000fa000 /* 1 MB in SRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
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/*
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* Low Level Configuration Settings
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*/
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/*
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* Internal Memory Mapped (This is not the IMMR content)
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*/
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#define CONFIG_SYS_IMMR 0x01000000 /* Physical start adress of internal memory map */
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/*
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* Definitions for initial stack pointer and data area
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
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#define CONFIG_SYS_INIT_RAM_END (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
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#define CONFIG_SYS_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */
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#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_RAM_ADDR) - CONFIG_SYS_GBL_DATA_SIZE) /* Offset from the beginning of ram */
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#define CONFIG_SYS_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */
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/*
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* Start addresses for the final memory configuration
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
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#define CONFIG_SYS_FLASH_BASE 0x02000000 /* External flash */
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#define PLD_BASE 0x03000000 /* PLD */
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#define ANYBUS_BASE 0x03010000 /* Anybus Module */
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#define CONFIG_SYS_RESET_ADRESS 0x01000000 /* Adress which causes reset */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */
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/* This adress is given to the linker with -Ttext to */
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/* locate the text section at this adress. */
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#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Physically section protection on */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
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#define CONFIG_ENV_SIZE 0x00010000 /* Set whole sector as env */
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#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWP)
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#endif /* CONFIG_WATCHDOG */
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CONFIG_SYS_PISCR (PISCR_PITF)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF00
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#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
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SCCR_COM00 | SCCR_DFNL000 | SCCR_DFNH000)
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration
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*-----------------------------------------------------------------------
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* Data show cycle
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*/
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#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register
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*-----------------------------------------------------------------------
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* Set all bits to 40 Mhz
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*
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*/
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#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
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#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
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/*-----------------------------------------------------------------------
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* UMCR - UIMB Module Configuration Register
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
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/*-----------------------------------------------------------------------
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* ICTRL - I-Bus Support Control Register
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*/
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#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
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/*-----------------------------------------------------------------------
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* USIU - Memory Controller Register
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
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#define CONFIG_SYS_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3)
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#define CONFIG_SYS_BR1_PRELIM (ANYBUS_BASE)
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#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_PS_32)
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#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF)
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#define CONFIG_SYS_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
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#define CONFIG_SYS_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
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OR_ACS_10 | OR_ETHR | OR_CSNT)
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#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */
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/*-----------------------------------------------------------------------
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* DER - Timer Decrementer
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*-----------------------------------------------------------------------
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* Initialise to zero
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*/
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#define CONFIG_SYS_DER 0x00000000
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#endif /* __CONFIG_H */
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