mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
d98b0523cf
Now that warm booting is not supported, there isn't a need for the BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them. Note that this change makes the board info bd_bootflags field useless. It will always be set to 0, but we leave it around so that we don't break the board info structure that some OSes are expecting to be passed from U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
342 lines
12 KiB
C
342 lines
12 KiB
C
/*
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* (C) Copyright 2000, 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2001
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* James F. Dougherty (jfd@cs.stanford.edu)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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*
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* Configuration settings for the MOUSSE board.
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* See also: http://www.vooha.com/
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*
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC824X 1
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#define CONFIG_MPC8240 1
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#define CONFIG_MOUSSE 1
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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#define CONFIG_SYS_ADDR_MAP_B 1
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 9600
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#if 1
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#define CONFIG_BOOTCOMMAND "tftp 100000 vmlinux.img;bootm" /* autoboot command */
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#else
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#define CONFIG_BOOTCOMMAND "bootm ffe10000"
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#endif
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#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
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#define CONFIG_BOOTDELAY 3
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DATE
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_ETH_ADDR "00:10:18:10:00:06"
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#define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */
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#include "../board/mousse/mousse.h"
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/*
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* Miscellaneous configurable options
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*/
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#undef CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#ifdef DEBUG
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_SDRAM_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#endif
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#ifdef DEBUG
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#define CONFIG_SYS_MONITOR_LEN (4 << 20) /* lots of mem ... */
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#else
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#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512K PLCC bootrom */
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#endif
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#define CONFIG_SYS_MALLOC_LEN (2*(4096 << 10)) /* 2*4096kB for malloc() */
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#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
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#define CONFIG_SYS_EUMB_ADDR 0xFC000000
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#define CONFIG_SYS_ISA_MEM 0xFD000000
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#define CONFIG_SYS_ISA_IO 0xFE000000
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#define CONFIG_SYS_FLASH_BASE 0xFFF00000
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#define CONFIG_SYS_FLASH_SIZE ((uint)(512 * 1024))
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#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
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#define FLASH_BASE0_PRELIM 0xFFF00000 /* 512K PLCC FLASH/AM29F040*/
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#define FLASH_BASE0_SIZE 0x80000 /* 512K */
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#define FLASH_BASE1_PRELIM 0xFFE10000 /* AMD 29LV160DB
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1MB - 64K FLASH0 SEG =960K
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(size=0xf0000)*/
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK 18432000
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#define CONFIG_SYS_NS16550_COM1 0xFFE08080
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
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#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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* For the detail description refer to the MPC8240 user's manual.
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*/
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#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
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#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_ETH_DEV_FN 0x00
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#define CONFIG_SYS_ETH_IOBASE 0x00104000
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/* Bit-field values for MCCR1.
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*/
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#define CONFIG_SYS_ROMNAL 8
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#define CONFIG_SYS_ROMFAL 8
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/* Bit-field values for MCCR2.
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*/
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#define CONFIG_SYS_REFINT 0xf5 /* Refresh interval */
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/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
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*/
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#define CONFIG_SYS_BSTOPRE 0x79
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#ifdef INCLUDE_ECC
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#define USE_ECC 1
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#else /* INCLUDE_ECC */
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#define USE_ECC 0
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#endif /* INCLUDE_ECC */
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/* Bit-field values for MCCR3.
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*/
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#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
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#define CONFIG_SYS_RDLAT (4+USE_ECC) /* Data latancy from read command */
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/* Bit-field values for MCCR4.
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*/
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#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
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#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
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#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
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#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
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#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
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#define CONFIG_SYS_ACTORW 2
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#define CONFIG_SYS_REGISTERD_TYPE_BUFFER (1-USE_ECC)
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/* Memory bank settings.
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* Only bits 20-29 are actually used from these vales to set the
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* start/end addresses. The upper two bits will always be 0, and the lower
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* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
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* address. Refer to the MPC8240 book.
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*/
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#define CONFIG_SYS_RAM_SIZE 0x04000000 /* 64MB */
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#define CONFIG_SYS_BANK0_START 0x00000000
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#define CONFIG_SYS_BANK0_END (CONFIG_SYS_RAM_SIZE - 1)
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#define CONFIG_SYS_BANK0_ENABLE 1
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#define CONFIG_SYS_BANK1_START 0x3ff00000
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#define CONFIG_SYS_BANK1_END 0x3fffffff
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#define CONFIG_SYS_BANK1_ENABLE 0
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#define CONFIG_SYS_BANK2_START 0x3ff00000
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#define CONFIG_SYS_BANK2_END 0x3fffffff
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#define CONFIG_SYS_BANK2_ENABLE 0
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#define CONFIG_SYS_BANK3_START 0x3ff00000
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#define CONFIG_SYS_BANK3_END 0x3fffffff
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#define CONFIG_SYS_BANK3_ENABLE 0
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#define CONFIG_SYS_BANK4_START 0x3ff00000
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#define CONFIG_SYS_BANK4_END 0x3fffffff
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#define CONFIG_SYS_BANK4_ENABLE 0
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#define CONFIG_SYS_BANK5_START 0x3ff00000
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#define CONFIG_SYS_BANK5_END 0x3fffffff
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#define CONFIG_SYS_BANK5_ENABLE 0
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#define CONFIG_SYS_BANK6_START 0x3ff00000
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#define CONFIG_SYS_BANK6_END 0x3fffffff
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#define CONFIG_SYS_BANK6_ENABLE 0
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#define CONFIG_SYS_BANK7_START 0x3ff00000
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#define CONFIG_SYS_BANK7_END 0x3fffffff
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#define CONFIG_SYS_BANK7_ENABLE 0
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#define CONFIG_SYS_ODCR 0x7f
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#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory
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see 8240 book for details*/
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#define PCI_MEM_SPACE1_START 0x80000000
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#define PCI_MEM_SPACE2_START 0xfd000000
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/* IBAT/DBAT Configuration */
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/* Ram: 64MB, starts at address-0, r/w instruction/data */
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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/* MPLD/Port-X I/O Space : data and instruction read/write, cache-inhibit */
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#define CONFIG_SYS_IBAT1U (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
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#if 0
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#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 | BATL_MEMCOHERENCE |\
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BATL_WRITETHROUGH | BATL_CACHEINHIBIT)
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#else
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#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
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#endif
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
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#define CONFIG_SYS_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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/* PCI Memory region 2: PCI Devices in 0xFD space */
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#define CONFIG_SYS_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* Max number of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#if 0
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */
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#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment Sector */
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#else
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#define CONFIG_ENV_IS_IN_NVRAM 1
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#define CONFIG_ENV_ADDR NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/
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#define CONFIG_ENV_OFFSET CONFIG_ENV_ADDR
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#define CONFIG_ENV_SIZE NV_U_BOOT_ENV_SIZE /* 2K */
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16
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/* Localizations */
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#if 0
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#define CONFIG_ETHADDR 0:0:0:0:1:d
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#define CONFIG_IPADDR 172.16.40.113
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#define CONFIG_SERVERIP 172.16.40.111
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#else
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#define CONFIG_ETHADDR 0:0:0:0:1:d
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#define CONFIG_IPADDR 209.128.93.138
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#define CONFIG_SERVERIP 209.128.93.133
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#endif
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_PCI /* include pci support */
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#undef CONFIG_PCI_PNP
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */
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#define CONFIG_TULIP
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#endif /* __CONFIG_H */
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