mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-15 06:33:45 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
362 lines
10 KiB
ArmAsm
362 lines
10 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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#include <asm/processor.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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wait_timer WAIT_200US
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wait_timer WAIT_200US
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/*------- LBSC -------*/
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write32 MMSELR_A, MMSELR_D
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/*------- DBSC2 -------*/
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write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D
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write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D
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write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D
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write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D
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write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1
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write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2
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wait_timer WAIT_200US
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write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D
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write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H
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wait_timer WAIT_200US
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write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1
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write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
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write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
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write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2
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wait_timer WAIT_200US
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
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write32 DBSC2_DBEN_A, DBSC2_DBEN_D
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write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D
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write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D
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write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D
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wait_timer WAIT_200US
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/*------- GPIO -------*/
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write16 PACR_A, PXCR_D
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write16 PBCR_A, PXCR_D
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write16 PCCR_A, PXCR_D
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write16 PDCR_A, PXCR_D
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write16 PECR_A, PXCR_D
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write16 PFCR_A, PXCR_D
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write16 PGCR_A, PXCR_D
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write16 PHCR_A, PHCR_D
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write16 PJCR_A, PJCR_D
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write16 PKCR_A, PKCR_D
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write16 PLCR_A, PXCR_D
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write16 PMCR_A, PMCR_D
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write16 PNCR_A, PNCR_D
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write16 PPCR_A, PXCR_D
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write16 PQCR_A, PXCR_D
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write16 PRCR_A, PXCR_D
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write8 PEPUPR_A, PEPUPR_D
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write8 PHPUPR_A, PHPUPR_D
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write8 PJPUPR_A, PJPUPR_D
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write8 PKPUPR_A, PKPUPR_D
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write8 PLPUPR_A, PLPUPR_D
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write8 PMPUPR_A, PMPUPR_D
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write8 PNPUPR_A, PNPUPR_D
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write16 PPUPR1_A, PPUPR1_D
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write16 PPUPR2_A, PPUPR2_D
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write16 P1MSELR_A, P1MSELR_D
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write16 P2MSELR_A, P2MSELR_D
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/*------- LBSC -------*/
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write32 BCR_A, BCR_D
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write32 CS0BCR_A, CS0BCR_D
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write32 CS0WCR_A, CS0WCR_D
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write32 CS1BCR_A, CS1BCR_D
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write32 CS1WCR_A, CS1WCR_D
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write32 CS4BCR_A, CS4BCR_D
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write32 CS4WCR_A, CS4WCR_D
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mov.l PASCR_A, r0
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mov.l @r0, r2
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mov.l PASCR_32BIT_MODE, r1
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tst r1, r2
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bt lbsc_29bit
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write32 CS2BCR_A, CS_USB_BCR_D
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write32 CS2WCR_A, CS_USB_WCR_D
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write32 CS3BCR_A, CS_SD_BCR_D
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write32 CS3WCR_A, CS_SD_WCR_D
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write32 CS5BCR_A, CS_I2C_BCR_D
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write32 CS5WCR_A, CS_I2C_WCR_D
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write32 CS6BCR_A, CS0BCR_D
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write32 CS6WCR_A, CS0WCR_D
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bra lbsc_end
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nop
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lbsc_29bit:
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write32 CS5BCR_A, CS_USB_BCR_D
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write32 CS5WCR_A, CS_USB_WCR_D
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write32 CS6BCR_A, CS_SD_BCR_D
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write32 CS6WCR_A, CS_SD_WCR_D
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lbsc_end:
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#if defined(CONFIG_SH_32BIT)
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/*------- set PMB -------*/
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write32 PASCR_A, PASCR_29BIT_D
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write32 MMUCR_A, MMUCR_D
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/*****************************************************************
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* ent virt phys v sz c wt
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* 0 0xa0000000 0x00000000 1 64M 0 0
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* 1 0xa4000000 0x04000000 1 16M 0 0
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* 2 0xa6000000 0x08000000 1 16M 0 0
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* 9 0x88000000 0x48000000 1 128M 1 1
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* 10 0x90000000 0x50000000 1 128M 1 1
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* 11 0x98000000 0x58000000 1 128M 1 1
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* 13 0xa8000000 0x48000000 1 128M 0 0
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* 14 0xb0000000 0x50000000 1 128M 0 0
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* 15 0xb8000000 0x58000000 1 128M 0 0
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*/
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write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D
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write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D
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write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D
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write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D
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write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D
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write32 PMB_DATA_USB_A, PMB_DATA_USB_D
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write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
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write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
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write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D
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write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D
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write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D
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write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D
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write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
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write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
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write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D
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write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D
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write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D
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write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D
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write32 PASCR_A, PASCR_INIT
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mov.l DUMMY_ADDR, r0
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icbi @r0
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#endif
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write32 CCR_A, CCR_D
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rts
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nop
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.align 4
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/*------- GPIO -------*/
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/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */
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PXCR_D: .word 0x0000
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PHCR_D: .word 0x00c0
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PJCR_D: .word 0xc3fc
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PKCR_D: .word 0x03ff
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PMCR_D: .word 0xffff
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PNCR_D: .word 0xf0c3
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PEPUPR_D: .long 0xff
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PHPUPR_D: .long 0x00
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PJPUPR_D: .long 0x00
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PKPUPR_D: .long 0x00
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PLPUPR_D: .long 0x00
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PMPUPR_D: .long 0xfc
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PNPUPR_D: .long 0x00
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PPUPR1_D: .word 0xffbf
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PPUPR2_D: .word 0xff00
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P1MSELR_D: .word 0x3780
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P2MSELR_D: .word 0x0000
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#define GPIO_BASE 0xffe70000
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PACR_A: .long GPIO_BASE + 0x00
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PBCR_A: .long GPIO_BASE + 0x02
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PCCR_A: .long GPIO_BASE + 0x04
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PDCR_A: .long GPIO_BASE + 0x06
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PECR_A: .long GPIO_BASE + 0x08
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PFCR_A: .long GPIO_BASE + 0x0a
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PGCR_A: .long GPIO_BASE + 0x0c
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PHCR_A: .long GPIO_BASE + 0x0e
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PJCR_A: .long GPIO_BASE + 0x10
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PKCR_A: .long GPIO_BASE + 0x12
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PLCR_A: .long GPIO_BASE + 0x14
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PMCR_A: .long GPIO_BASE + 0x16
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PNCR_A: .long GPIO_BASE + 0x18
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PPCR_A: .long GPIO_BASE + 0x1a
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PQCR_A: .long GPIO_BASE + 0x1c
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PRCR_A: .long GPIO_BASE + 0x1e
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PEPUPR_A: .long GPIO_BASE + 0x48
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PHPUPR_A: .long GPIO_BASE + 0x4e
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PJPUPR_A: .long GPIO_BASE + 0x50
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PKPUPR_A: .long GPIO_BASE + 0x52
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PLPUPR_A: .long GPIO_BASE + 0x54
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PMPUPR_A: .long GPIO_BASE + 0x56
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PNPUPR_A: .long GPIO_BASE + 0x58
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PPUPR1_A: .long GPIO_BASE + 0x60
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PPUPR2_A: .long GPIO_BASE + 0x62
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P1MSELR_A: .long GPIO_BASE + 0x80
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P2MSELR_A: .long GPIO_BASE + 0x82
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MMSELR_A: .long 0xfc400020
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#if defined(CONFIG_SH_32BIT)
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MMSELR_D: .long 0xa5a50005
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#else
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MMSELR_D: .long 0xa5a50002
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#endif
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/*------- DBSC2 -------*/
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#define DBSC2_BASE 0xfe800000
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DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
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DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
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DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
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DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
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DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
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DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
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DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
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DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
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DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
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DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
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DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
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DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
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DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54
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DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
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DDR_DUMMY_ACCESS_A: .long 0x40000000
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DBSC2_DBCONF_D: .long 0x00630002
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DBSC2_DBTR0_D: .long 0x050b1f04
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DBSC2_DBTR1_D: .long 0x00040204
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DBSC2_DBTR2_D: .long 0x02100308
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DBSC2_DBFREQ_D1: .long 0x00000000
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DBSC2_DBFREQ_D2: .long 0x00000100
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DBSC2_DBDICODTOCD_D:.long 0x000f0907
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DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
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DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
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DBSC2_DBCMDCNT_D_REF: .long 0x00000004
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DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
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DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
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DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
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DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
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DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
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DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
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DBSC2_DBEN_D: .long 0x00000001
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DBSC2_DBPDCNT0_D3: .long 0x00000080
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DBSC2_DBRFCNT1_D: .long 0x00000926
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DBSC2_DBRFCNT2_D: .long 0x00fe00fe
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DBSC2_DBRFCNT0_D: .long 0x00010000
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WAIT_200US: .long 33333
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/*------- LBSC -------*/
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PASCR_A: .long 0xff000070
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PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
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BCR_A: .long BCR
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CS0BCR_A: .long CS0BCR
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CS0WCR_A: .long CS0WCR
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CS1BCR_A: .long CS1BCR
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CS1WCR_A: .long CS1WCR
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CS2BCR_A: .long CS2BCR
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CS2WCR_A: .long CS2WCR
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CS3BCR_A: .long CS3BCR
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CS3WCR_A: .long CS3WCR
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CS4BCR_A: .long CS4BCR
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CS4WCR_A: .long CS4WCR
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CS5BCR_A: .long CS5BCR
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CS5WCR_A: .long CS5WCR
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CS6BCR_A: .long CS6BCR
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CS6WCR_A: .long CS6WCR
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BCR_D: .long 0x80000003
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CS0BCR_D: .long 0x22222340
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CS0WCR_D: .long 0x00111118
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CS1BCR_D: .long 0x11111100
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CS1WCR_D: .long 0x33333303
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CS4BCR_D: .long 0x11111300
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CS4WCR_D: .long 0x00101012
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/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
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CS_USB_BCR_D: .long 0x11111200
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CS_USB_WCR_D: .long 0x00020005
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/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
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CS_SD_BCR_D: .long 0x00000300
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CS_SD_WCR_D: .long 0x00030108
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/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
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CS_I2C_BCR_D: .long 0x11111100
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CS_I2C_WCR_D: .long 0x00000003
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#if defined(CONFIG_SH_32BIT)
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/*------- set PMB -------*/
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PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0)
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PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1)
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PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2)
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PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9)
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PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10)
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PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11)
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PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13)
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PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14)
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PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15)
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PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0)
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PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4)
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PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6)
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PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
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PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90)
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PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98)
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PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
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PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0)
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PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8)
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PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0)
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PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1)
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PMB_DATA_USB_A: .long PMB_DATA_BASE(2)
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PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9)
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PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10)
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PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11)
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PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13)
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PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14)
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PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15)
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/* ppn ub v s1 s0 c wt */
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PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
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PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
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PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
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PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
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PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
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PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
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PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
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PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
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PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
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DUMMY_ADDR: .long 0xa0000000
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PASCR_29BIT_D: .long 0x00000000
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PASCR_INIT: .long 0x80000080 /* check booting mode */
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MMUCR_A: .long 0xff000010
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MMUCR_D: .long 0x00000004 /* clear ITLB */
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#endif /* CONFIG_SH_32BIT */
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CCR_A: .long 0xff00001c
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CCR_D: .long 0x0000090b
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