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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-15 06:33:45 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
338 lines
9.1 KiB
C
338 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* K+P iMX6Q KP_IMX6Q_TPC board configuration
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*
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* Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <fuse.h>
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#include <fsl_esdhc.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <spl.h>
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#define UART_PAD_CTRL \
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(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL \
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(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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DECLARE_GLOBAL_DATA_PTR;
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC03, &ccm->CCGR1);
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writel(0x0FFFC000, &ccm->CCGR2);
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writel(0x3FF00000, &ccm->CCGR3);
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writel(0x00FFF300, &ccm->CCGR4);
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writel(0x0F0000C3, &ccm->CCGR5);
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writel(0x000003FF, &ccm->CCGR6);
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}
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/* onboard microSD */
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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/* eMMC */
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static iomux_v3_cfg_t const usdhc4_pads[] = {
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IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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};
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/* SD */
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static void setup_iomux_sd(void)
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{
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SETUP_IOMUX_PADS(usdhc2_pads);
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SETUP_IOMUX_PADS(usdhc4_pads);
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}
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/* UART */
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static iomux_v3_cfg_t const uart1_pads[] = {
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IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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static void setup_iomux_uart(void)
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{
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SETUP_IOMUX_PADS(uart1_pads);
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}
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/* USB */
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static iomux_v3_cfg_t const usb_pads[] = {
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IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static void setup_iomux_usb(void)
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{
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SETUP_IOMUX_PADS(usb_pads);
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}
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/* DDR3 */
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static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_sdclk_0 = 0x00000030,
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.dram_sdclk_1 = 0x00000030,
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.dram_cas = 0x00000030,
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.dram_ras = 0x00000030,
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.dram_reset = 0x00000030,
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x00000030,
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.dram_sdodt1 = 0x00000030,
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.dram_sdqs0 = 0x00000018,
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.dram_sdqs1 = 0x00000018,
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.dram_sdqs2 = 0x00000018,
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.dram_sdqs3 = 0x00000018,
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.dram_sdqs4 = 0x00000018,
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.dram_sdqs5 = 0x00000018,
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.dram_sdqs6 = 0x00000018,
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.dram_sdqs7 = 0x00000018,
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.dram_dqm0 = 0x00000018,
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.dram_dqm1 = 0x00000018,
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.dram_dqm2 = 0x00000018,
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.dram_dqm3 = 0x00000018,
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.dram_dqm4 = 0x00000018,
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.dram_dqm5 = 0x00000018,
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.dram_dqm6 = 0x00000018,
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.dram_dqm7 = 0x00000018,
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};
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static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000018,
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.grp_b1ds = 0x00000018,
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.grp_b2ds = 0x00000018,
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.grp_b3ds = 0x00000018,
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.grp_b4ds = 0x00000018,
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.grp_b5ds = 0x00000018,
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.grp_b6ds = 0x00000018,
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.grp_b7ds = 0x00000018,
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};
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static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
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.p0_mpwldectrl0 = 0x001F001F,
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.p0_mpwldectrl1 = 0x001F001F,
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.p1_mpwldectrl0 = 0x001F001F,
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.p1_mpwldectrl1 = 0x001F001F,
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.p0_mpdgctrl0 = 0x43270338,
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.p0_mpdgctrl1 = 0x03200314,
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.p1_mpdgctrl0 = 0x431A032F,
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.p1_mpdgctrl1 = 0x03200263,
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.p0_mprddlctl = 0x4B434748,
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.p1_mprddlctl = 0x4445404C,
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.p0_mpwrdlctl = 0x38444542,
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.p1_mpwrdlctl = 0x4935493A,
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};
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/* MT41K256M16 (4Gb density) */
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static const struct mx6_ddr3_cfg mt41k256m16 = {
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.mem_speed = 1600,
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.density = 4,
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.width = 16,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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#ifdef CONFIG_MX6_DDRCAL
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static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
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{
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struct mx6_mmdc_calibration calibration = {0};
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mmdc_read_calibration(sysinfo, &calibration);
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debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
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debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
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debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
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debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
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debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
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debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
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debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
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debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
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debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
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debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
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debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
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debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
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}
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static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
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{
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int ret;
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/* Perform DDR DRAM calibration */
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udelay(100);
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ret = mmdc_do_write_level_calibration(sysinfo);
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if (ret) {
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printf("DDR: Write level calibration error [%d]\n", ret);
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return;
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}
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ret = mmdc_do_dqs_calibration(sysinfo);
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if (ret) {
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printf("DDR: DQS calibration error [%d]\n", ret);
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return;
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}
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spl_dram_print_cal(sysinfo);
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}
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#endif /* CONFIG_MX6_DDRCAL */
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static void spl_dram_init(void)
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{
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struct mx6_ddr_sysinfo sysinfo = {
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/* width of data bus:0=16,1=32,2=64 */
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.dsize = 2,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32, /* 32Gb per CS */
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/* single chip select */
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
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.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.pd_fast_exit = 1, /* enable precharge power-down fast exit */
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.ddr_type = DDR_TYPE_DDR3,
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.refsel = 1, /* Refresh cycles at 32KHz */
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.refr = 7, /* 8 refresh commands per refresh cycle */
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};
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mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16);
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#ifdef CONFIG_MX6_DDRCAL
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spl_dram_perform_cal(&sysinfo);
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#endif
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}
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struct fsl_esdhc_cfg usdhc_cfg[] = {
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{USDHC2_BASE_ADDR},
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{USDHC4_BASE_ADDR},
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};
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#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC2_BASE_ADDR:
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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break;
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case USDHC4_BASE_ADDR:
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ret = 1; /* eMMC/uSDHC4 is always present */
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bd)
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{
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struct src *psrc = (struct src *)SRC_BASE_ADDR;
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unsigned int reg = readl(&psrc->sbmr1) >> 11;
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/*
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* Upon reading BOOT_CFG register the following map is done:
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* Bit 11 and 12 of BOOT_CFG register can determine the current
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* mmc port
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* 0x1 SD1
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* 0x3 SD4
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*/
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switch (reg & 0x3) {
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case 0x1:
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SETUP_IOMUX_PADS(usdhc2_pads);
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usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
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break;
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case 0x3:
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SETUP_IOMUX_PADS(usdhc4_pads);
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usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
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break;
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}
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return fsl_esdhc_initialize(bd, &usdhc_cfg[0]);
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}
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void board_init_f(ulong dummy)
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{
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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ccgr_init();
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gpr_init();
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/* setup GP timer */
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timer_init();
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setup_iomux_sd();
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setup_iomux_uart();
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setup_iomux_usb();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* DDR initialization */
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spl_dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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}
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