mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-15 06:33:45 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
509 lines
10 KiB
C
509 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/ls102xa_soc.h>
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#include <asm/arch/ls102xa_devdis.h>
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#include <asm/arch/ls102xa_sata.h>
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#include <hwconfig.h>
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#include <mmc.h>
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#include <fsl_csu.h>
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#include <fsl_esdhc.h>
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#include <fsl_ifc.h>
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#include <fsl_sec.h>
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#include <spl.h>
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#include <fsl_devdis.h>
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#include <fsl_validate.h>
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#include <fsl_ddr.h>
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#include "../common/sleep.h"
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#include "../common/qixis.h"
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#include "ls1021aqds_qixis.h"
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#ifdef CONFIG_U_QE
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#include <fsl_qe.h>
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#endif
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#define PIN_MUX_SEL_CAN 0x03
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#define PIN_MUX_SEL_IIC2 0xa0
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#define PIN_MUX_SEL_RGMII 0x00
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#define PIN_MUX_SEL_SAI 0x0c
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#define PIN_MUX_SEL_SDHC 0x00
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#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
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#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
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enum {
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MUX_TYPE_CAN,
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MUX_TYPE_IIC2,
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MUX_TYPE_RGMII,
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MUX_TYPE_SAI,
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MUX_TYPE_SDHC,
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MUX_TYPE_SD_PCI4,
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MUX_TYPE_SD_PC_SA_SG_SG,
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MUX_TYPE_SD_PC_SA_PC_SG,
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MUX_TYPE_SD_PC_SG_SG,
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};
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enum {
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GE0_CLK125,
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GE2_CLK125,
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GE1_CLK125,
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};
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int checkboard(void)
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{
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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char buf[64];
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#endif
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#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
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u8 sw;
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#endif
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puts("Board: LS1021AQDS\n");
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#ifdef CONFIG_SD_BOOT
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puts("SD\n");
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#elif CONFIG_QSPI_BOOT
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puts("QSPI\n");
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#else
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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printf("vBank: %d\n", sw);
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else if (sw == 0x8)
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puts("PromJet\n");
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else if (sw == 0x9)
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puts("NAND\n");
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else if (sw == 0x15)
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printf("IFCCard\n");
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else
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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#endif
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
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QIXIS_READ(id), QIXIS_READ(arch));
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printf("FPGA: v%d (%s), build %d\n",
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(int)QIXIS_READ(scver), qixis_read_tag(buf),
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(int)qixis_read_minor());
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#endif
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return 0;
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch (sysclk_conf & 0x0f) {
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case QIXIS_SYSCLK_64:
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return 64000000;
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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switch ((ddrclk_conf & 0x30) >> 4) {
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case QIXIS_DDRCLK_100:
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return 100000000;
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case QIXIS_DDRCLK_125:
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return 125000000;
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case QIXIS_DDRCLK_133:
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return 133333333;
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}
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return 66666666;
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}
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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int dram_init(void)
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{
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/*
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* When resuming from deep sleep, the I2C channel may not be
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* in the default channel. So, switch to the default channel
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* before accessing DDR SPD.
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*/
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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return fsl_initdram();
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[1] = {
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{CONFIG_SYS_FSL_ESDHC_ADDR},
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};
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int board_mmc_init(bd_t *bis)
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{
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
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}
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#endif
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int board_early_init_f(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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#ifdef CONFIG_TSEC_ENET
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/* clear BD & FR bits for BE BD's and frame data */
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clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
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#endif
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#ifdef CONFIG_FSL_IFC
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init_early_memctl_regs();
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#endif
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arch_soc_init();
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#if defined(CONFIG_DEEP_SLEEP)
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if (is_warm_boot())
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fsl_dp_disable_console();
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#endif
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
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CONFIG_SYS_CCI400_OFFSET);
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unsigned int major;
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#ifdef CONFIG_NAND_BOOT
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 porsr1, pinctl;
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/*
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* There is LS1 SoC issue where NOR, FPGA are inaccessible during
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* NAND boot because IFC signals > IFC_AD7 are not enabled.
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* This workaround changes RCW source to make all signals enabled.
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*/
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porsr1 = in_be32(&gur->porsr1);
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pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
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DCFG_CCSR_PORSR1_RCW_SRC_I2C);
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out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
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pinctl);
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#endif
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/* Clear the BSS */
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memset(__bss_start, 0, __bss_end - __bss_start);
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#ifdef CONFIG_FSL_IFC
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init_early_memctl_regs();
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#endif
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get_clocks();
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#if defined(CONFIG_DEEP_SLEEP)
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if (is_warm_boot())
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fsl_dp_disable_console();
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#endif
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preloader_console_init();
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#ifdef CONFIG_SPL_I2C_SUPPORT
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i2c_init_all();
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#endif
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major = get_soc_major_rev();
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if (major == SOC_MAJOR_VER_1_0)
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
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dram_init();
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/* Allow OCRAM access permission as R/W */
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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board_init_r(NULL, 0);
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}
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#endif
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void config_etseccm_source(int etsec_gtx_125_mux)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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switch (etsec_gtx_125_mux) {
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case GE0_CLK125:
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out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
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debug("etseccm set to GE0_CLK125\n");
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break;
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case GE2_CLK125:
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out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
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debug("etseccm set to GE2_CLK125\n");
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break;
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case GE1_CLK125:
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out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
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debug("etseccm set to GE1_CLK125\n");
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break;
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default:
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printf("Error! trying to set etseccm to invalid value\n");
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break;
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}
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}
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int config_board_mux(int ctrl_type)
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{
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u8 reg12, reg14;
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reg12 = QIXIS_READ(brdcfg[12]);
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reg14 = QIXIS_READ(brdcfg[14]);
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switch (ctrl_type) {
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case MUX_TYPE_CAN:
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config_etseccm_source(GE2_CLK125);
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reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
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break;
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case MUX_TYPE_IIC2:
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reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
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break;
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case MUX_TYPE_RGMII:
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reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
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break;
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case MUX_TYPE_SAI:
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config_etseccm_source(GE2_CLK125);
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reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
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break;
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case MUX_TYPE_SDHC:
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reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
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break;
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case MUX_TYPE_SD_PCI4:
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reg12 = 0x38;
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break;
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case MUX_TYPE_SD_PC_SA_SG_SG:
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reg12 = 0x01;
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break;
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case MUX_TYPE_SD_PC_SA_PC_SG:
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reg12 = 0x01;
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break;
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case MUX_TYPE_SD_PC_SG_SG:
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reg12 = 0x21;
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break;
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default:
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printf("Wrong mux interface type\n");
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return -1;
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}
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QIXIS_WRITE(brdcfg[12], reg12);
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QIXIS_WRITE(brdcfg[14], reg14);
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return 0;
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}
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int config_serdes_mux(void)
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{
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struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 cfg;
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cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
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cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
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switch (cfg) {
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case 0x0:
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config_board_mux(MUX_TYPE_SD_PCI4);
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break;
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case 0x30:
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config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
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break;
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case 0x60:
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config_board_mux(MUX_TYPE_SD_PC_SG_SG);
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break;
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case 0x70:
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config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
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break;
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default:
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printf("SRDS1 prtcl:0x%x\n", cfg);
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break;
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}
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_SCSI_AHCI_PLAT
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ls1021a_sata_init();
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#endif
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#ifdef CONFIG_CHAIN_OF_TRUST
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fsl_setenv_chain_of_trust();
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#endif
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return 0;
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}
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#endif
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int misc_init_r(void)
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{
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int conflict_flag;
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/* some signals can not enable simultaneous*/
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conflict_flag = 0;
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if (hwconfig("sdhc"))
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conflict_flag++;
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if (hwconfig("iic2"))
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conflict_flag++;
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if (conflict_flag > 1) {
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printf("WARNING: pin conflict !\n");
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return 0;
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}
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conflict_flag = 0;
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if (hwconfig("rgmii"))
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conflict_flag++;
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if (hwconfig("can"))
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conflict_flag++;
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if (hwconfig("sai"))
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conflict_flag++;
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if (conflict_flag > 1) {
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printf("WARNING: pin conflict !\n");
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return 0;
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}
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if (hwconfig("can"))
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config_board_mux(MUX_TYPE_CAN);
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else if (hwconfig("rgmii"))
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config_board_mux(MUX_TYPE_RGMII);
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else if (hwconfig("sai"))
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config_board_mux(MUX_TYPE_SAI);
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if (hwconfig("iic2"))
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config_board_mux(MUX_TYPE_IIC2);
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else if (hwconfig("sdhc"))
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config_board_mux(MUX_TYPE_SDHC);
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#ifdef CONFIG_FSL_DEVICE_DISABLE
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device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
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#endif
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#ifdef CONFIG_FSL_CAAM
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return sec_init();
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#endif
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return 0;
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}
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int board_init(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
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CONFIG_SYS_CCI400_OFFSET);
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unsigned int major;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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erratum_a010315();
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
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erratum_a009942_check_cpo();
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#endif
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major = get_soc_major_rev();
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if (major == SOC_MAJOR_VER_1_0) {
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/* Set CCI-400 control override register to
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* enable barrier transaction */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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}
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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#ifndef CONFIG_SYS_FSL_NO_SERDES
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fsl_serdes_init();
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config_serdes_mux();
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#endif
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ls102xa_smmu_stream_id_init();
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#ifdef CONFIG_U_QE
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u_qe_init();
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#endif
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return 0;
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}
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#if defined(CONFIG_DEEP_SLEEP)
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void board_sleep_prepare(void)
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{
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struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
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CONFIG_SYS_CCI400_OFFSET);
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unsigned int major;
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major = get_soc_major_rev();
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if (major == SOC_MAJOR_VER_1_0) {
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/* Set CCI-400 control override register to
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* enable barrier transaction */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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}
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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}
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#endif
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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u8 flash_read8(void *addr)
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{
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return __raw_readb(addr + 1);
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}
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void flash_write16(u16 val, void *addr)
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{
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u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
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__raw_writew(shftval, addr);
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}
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u16 flash_read16(void *addr)
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{
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u16 val = __raw_readw(addr);
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return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
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}
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