mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
d98b0523cf
Now that warm booting is not supported, there isn't a need for the BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them. Note that this change makes the board info bd_bootflags field useless. It will always be set to 0, but we leave it around so that we don't break the board info structure that some OSes are expecting to be passed from U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
825 lines
28 KiB
C
825 lines
28 KiB
C
/*
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* (C) Copyright 2000
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* Murray Jensen <Murray.Jensen@cmst.csiro.au>
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*
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* (C) Copyright 2000
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2001
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* Advent Networks, Inc. <http://www.adventnetworks.com>
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* Jay Monkman <jmonkman@adventnetworks.com>
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*
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* (C) Copyright 2001
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* Advent Networks, Inc. <http://www.adventnetworks.com>
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* Oliver Brown <obrown@adventnetworks.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*********************************************************************/
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/* DESCRIPTION:
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* This file contains the board configuartion for the GW8260 board.
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*
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* MODULE DEPENDENCY:
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* None
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*
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* RESTRICTIONS/LIMITATIONS:
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* None
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*
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* Copyright (c) 2001, Advent Networks, Inc.
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*/
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/*********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_TEXT_BASE 0x40000000
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/* Enable debug prints */
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#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
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/* What is the oscillator's (UX2) frequency in Hz? */
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#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
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/*-----------------------------------------------------------------------
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* MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
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*-----------------------------------------------------------------------
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* What should MODCK_H be? It is dependent on the oscillator
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* frequency, MODCK[1-3], and desired CPM and core frequencies.
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* Here are some example values (all frequencies are in MHz):
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*
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* MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
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* ------- ---------- --- --- ---- ----- ----- -----
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* 0x5 0x5 66 133 133 Open Close Open
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* 0x5 0x6 66 133 166 Open Open Close
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* 0x5 0x7 66 133 200 Open Open Open
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* 0x6 0x0 66 133 233 Close Close Close
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* 0x6 0x1 66 133 266 Close Close Open
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* 0x6 0x2 66 133 300 Close Open Close
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*/
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#define CONFIG_SYS_SBC_MODCK_H 0x05
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/* Define this if you want to boot from 0x00000100. If you don't define
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* this, you will need to program the bootloader to 0xfff00000, and
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* get the hardware reset config words at 0xfe000000. The simplest
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* way to do that is to program the bootloader at both addresses.
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* It is suggested that you just let U-Boot live at 0x00000000.
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*/
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#define CONFIG_SYS_SBC_BOOT_LOW 1
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/* What should the base address of the main FLASH be and how big is
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* it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sbc8260/config.mk
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* The main FLASH is whichever is connected to *CS0. U-Boot expects
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* this to be the SIMM.
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*/
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#define CONFIG_SYS_FLASH0_BASE 0x40000000
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#define CONFIG_SYS_FLASH0_SIZE 8
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/* Define CONFIG_SYS_FLASH_CHECKSUM to enable flash checksum during boot.
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* Note: the 'flashchecksum' environment variable must also be set to 'y'.
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*/
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#define CONFIG_SYS_FLASH_CHECKSUM
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/* What should be the base address of SDRAM DIMM and how big is
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* it (in Mbytes)?
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*/
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#define CONFIG_SYS_SDRAM0_BASE 0x00000000
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#define CONFIG_SYS_SDRAM0_SIZE 64
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/*
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* DRAM tests
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* CONFIG_SYS_DRAM_TEST - enables the following tests.
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*
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* CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
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* Environment variable 'test_dram_data' must be
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* set to 'y'.
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* CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
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* addressable. Environment variable
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* 'test_dram_address' must be set to 'y'.
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* CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
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* This test takes about 6 minutes to test 64 MB.
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* Environment variable 'test_dram_walk' must be
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* set to 'y'.
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*/
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#define CONFIG_SYS_DRAM_TEST
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#if defined(CONFIG_SYS_DRAM_TEST)
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#define CONFIG_SYS_DRAM_TEST_DATA
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#define CONFIG_SYS_DRAM_TEST_ADDRESS
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#define CONFIG_SYS_DRAM_TEST_WALK
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#endif /* CONFIG_SYS_DRAM_TEST */
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/*
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* GW8260 with 16 MB DIMM:
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*
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* 0x0000 0000 Exception Vector code, 8k
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* :
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* 0x0000 1FFF
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* 0x0000 2000 Free for Application Use
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* :
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* :
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*
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* :
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* :
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* 0x00F5 FF30 Monitor Stack (Growing downward)
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* Monitor Stack Buffer (0x80)
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* 0x00F5 FFB0 Board Info Data
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* 0x00F6 0000 Malloc Arena
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* : CONFIG_ENV_SECT_SIZE, 256k
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* : CONFIG_SYS_MALLOC_LEN, 128k
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* 0x00FC 0000 RAM Copy of Monitor Code
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* : CONFIG_SYS_MONITOR_LEN, 256k
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* 0x00FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
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*/
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/*
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* GW8260 with 64 MB DIMM:
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*
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* 0x0000 0000 Exception Vector code, 8k
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* :
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* 0x0000 1FFF
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* 0x0000 2000 Free for Application Use
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* :
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* :
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*
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* :
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* :
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* 0x03F5 FF30 Monitor Stack (Growing downward)
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* Monitor Stack Buffer (0x80)
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* 0x03F5 FFB0 Board Info Data
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* 0x03F6 0000 Malloc Arena
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* : CONFIG_ENV_SECT_SIZE, 256k
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* : CONFIG_SYS_MALLOC_LEN, 128k
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* 0x03FC 0000 RAM Copy of Monitor Code
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* : CONFIG_SYS_MONITOR_LEN, 256k
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* 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
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*/
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/*
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* select serial console configuration
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*
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* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*
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* if CONFIG_CONS_NONE is defined, then the serial console routines must
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* defined elsewhere.
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*/
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#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
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#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on neither */
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#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
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/*
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* select ethernet configuration
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*
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* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC)
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*
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
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* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
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*/
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#undef CONFIG_ETHER_ON_SCC
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#define CONFIG_ETHER_ON_FCC
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#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
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#ifdef CONFIG_ETHER_ON_SCC
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#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
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#endif /* CONFIG_ETHER_ON_SCC */
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#ifdef CONFIG_ETHER_ON_FCC
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#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
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/*
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* Port pins used for bit-banged MII communictions (if applicable).
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*/
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#define MDIO_PORT 2 /* Port C */
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#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
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(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
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#define MDC_DECLARE MDIO_DECLARE
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#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
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#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
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#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
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#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
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else iop->pdat &= ~0x00400000
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#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
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else iop->pdat &= ~0x00200000
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#define MIIDELAY udelay(1)
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#endif /* CONFIG_ETHER_ON_FCC */
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#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
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/*
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* - Rx-CLK is CLK13
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* - Tx-CLK is CLK14
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* - Select bus for bd/buffers (see 28-13)
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* - Enable Full Duplex in FSMR
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*/
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# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
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# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
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# define CONFIG_SYS_CPMFCR_RAMTYPE 0
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# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
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#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
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/*
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* - Rx-CLK is CLK15
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* - Tx-CLK is CLK16
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* - Select bus for bd/buffers (see 28-13)
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* - Enable Full Duplex in FSMR
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*/
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# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
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# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
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# define CONFIG_SYS_CPMFCR_RAMTYPE 0
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# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
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#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
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/* Define this to reserve an entire FLASH sector (256 KB) for
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* environment variables. Otherwise, the environment will be
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* put in the same sector as U-Boot, and changing variables
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* will erase U-Boot temporarily
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*/
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#define CONFIG_ENV_IN_OWN_SECT
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/* Define to allow the user to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* What should the console's baud rate be? */
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#define CONFIG_BAUDRATE 115200
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/* Ethernet MAC address - This is set to all zeros to force an
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* an error if we use BOOTP without setting
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* the MAC address
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*/
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#define CONFIG_ETHADDR 00:00:00:00:00:00
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/* Set to a positive value to delay for running BOOTCOMMAND */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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/* Be selective on what keys can delay or stop the autoboot process
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* To stop use: " "
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*/
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_PROMPT \
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"Autobooting in %d seconds, press \" \" to stop\n", bootdelay
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#define CONFIG_AUTOBOOT_STOP_STR " "
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#undef CONFIG_AUTOBOOT_DELAY_STR
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#define DEBUG_BOOTKEYS 0
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_DNS
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/* undef this to save memory */
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#define CONFIG_SYS_LONGHELP
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/* Monitor Command Prompt */
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#define CONFIG_SYS_PROMPT "=> "
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BEDBUG
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_IMMAP
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#define CONFIG_CMD_MII
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#undef CONFIG_CMD_KGDB
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/* Where do the internal registers live? */
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#define CONFIG_SYS_IMMR 0xf0000000
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#endif
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/* What is the address of IO controller */
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#define CONFIG_SYS_IO_BASE 0xe0000000
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/*****************************************************************************
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*
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* You should not have to modify any of the following settings
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*
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*****************************************************************************/
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#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
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#define CONFIG_GW8260 1 /* on an GW8260 Board */
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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/*
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* Miscellaneous configurable options
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*/
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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/* Convert clocks to MHZ when passing board info to kernel.
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* This must be defined for eariler 2.4 kernels (~2.4.4).
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*/
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#define CONFIG_CLOCKS_IN_MHZ
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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/* memtest works from the end of the exception vector table
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* to the end of the DRAM less monitor and malloc area
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*/
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#define CONFIG_SYS_MEMTEST_START 0x2000
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#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
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#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
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+ CONFIG_SYS_MALLOC_LEN \
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+ CONFIG_ENV_SECT_SIZE \
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+ CONFIG_SYS_STACK_USAGE )
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#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
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- CONFIG_SYS_MEM_END_USAGE )
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
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#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
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#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
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/*-----------------------------------------------------------------------
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* Hard Reset Configuration Words
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*/
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#if defined(CONFIG_SYS_SBC_BOOT_LOW)
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# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
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#else
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# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
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#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
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/* get the HRCW ISB field from CONFIG_SYS_IMMR */
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#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
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((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
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((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
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#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS11 | \
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HRCW_DPPC11 | \
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CONFIG_SYS_SBC_HRCW_IMMR | \
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HRCW_MMR00 | \
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HRCW_LBPC11 | \
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HRCW_APPC10 | \
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HRCW_CS10PC00 | \
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(CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
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CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
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/* no slaves */
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#define CONFIG_SYS_HRCW_SLAVE1 0
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#define CONFIG_SYS_HRCW_SLAVE2 0
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#define CONFIG_SYS_HRCW_SLAVE3 0
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#define CONFIG_SYS_HRCW_SLAVE4 0
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#define CONFIG_SYS_HRCW_SLAVE5 0
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#define CONFIG_SYS_HRCW_SLAVE6 0
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#define CONFIG_SYS_HRCW_SLAVE7 0
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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* Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
|
|
* FLASH and environment organization
|
|
*/
|
|
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
|
#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
|
|
|
|
#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
|
|
#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
|
|
|
|
#define CONFIG_ENV_IS_IN_FLASH 1
|
|
|
|
#ifdef CONFIG_ENV_IN_OWN_SECT
|
|
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + (256 * 1024))
|
|
# define CONFIG_ENV_SECT_SIZE (256 * 1024)
|
|
#else
|
|
# define CONFIG_ENV_SIZE (16 * 1024)/* Size of Environment Sector */
|
|
# define CONFIG_ENV_ADD ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SIZE)
|
|
# define CONFIG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size */
|
|
#endif /* CONFIG_ENV_IN_OWN_SECT */
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Cache Configuration
|
|
*/
|
|
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
|
#endif
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* HIDx - Hardware Implementation-dependent Registers 2-11
|
|
*-----------------------------------------------------------------------
|
|
* HID0 also contains cache control - initially enable both caches and
|
|
* invalidate contents, then the final state leaves only the instruction
|
|
* cache enabled. Note that Power-On and Hard reset invalidate the caches,
|
|
* but Soft reset does not.
|
|
*
|
|
* HID1 has only read-only information - nothing to set.
|
|
*/
|
|
#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
|
|
HID0_DCE |\
|
|
HID0_ICFI |\
|
|
HID0_DCI |\
|
|
HID0_IFEM |\
|
|
HID0_ABE)
|
|
|
|
#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
|
|
HID0_IFEM |\
|
|
HID0_ABE |\
|
|
HID0_EMCP)
|
|
#define CONFIG_SYS_HID2 0
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* RMR - Reset Mode Register
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
#define CONFIG_SYS_RMR 0
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* BCR - Bus Configuration 4-25
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
#define CONFIG_SYS_BCR (BCR_ETM)
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* SIUMCR - SIU Module Configuration 4-31
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
|
|
SIUMCR_L2CPC00 |\
|
|
SIUMCR_APPC10 |\
|
|
SIUMCR_MMR00)
|
|
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* SYPCR - System Protection Control 11-9
|
|
* SYPCR can only be written once after reset!
|
|
*-----------------------------------------------------------------------
|
|
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
|
|
*/
|
|
#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
|
|
SYPCR_BMT |\
|
|
SYPCR_PBME |\
|
|
SYPCR_LBME |\
|
|
SYPCR_SWRI |\
|
|
SYPCR_SWP)
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* TMCNTSC - Time Counter Status and Control 4-40
|
|
*-----------------------------------------------------------------------
|
|
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
|
|
* and enable Time Counter
|
|
*/
|
|
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
|
|
TMCNTSC_ALR |\
|
|
TMCNTSC_TCF |\
|
|
TMCNTSC_TCE)
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PISCR - Periodic Interrupt Status and Control 4-42
|
|
*-----------------------------------------------------------------------
|
|
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
|
* Periodic timer
|
|
*/
|
|
#define CONFIG_SYS_PISCR (PISCR_PS |\
|
|
PISCR_PTF |\
|
|
PISCR_PTE)
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* SCCR - System Clock Control 9-8
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
#define CONFIG_SYS_SCCR 0
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* RCCR - RISC Controller Configuration 13-7
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
#define CONFIG_SYS_RCCR 0
|
|
|
|
/*
|
|
* Initialize Memory Controller:
|
|
*
|
|
* Bank Bus Machine PortSz Device
|
|
* ---- --- ------- ------ ------
|
|
* 0 60x GPCM 32 bit FLASH (SIMM - 4MB)
|
|
* 1 60x GPCM 32 bit unused
|
|
* 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
|
|
* 3 60x SDRAM 64 bit unused
|
|
* 4 Local GPCM 8 bit IO (on board - 64k)
|
|
* 5 60x GPCM 8 bit unused
|
|
* 6 60x GPCM 8 bit unused
|
|
* 7 60x GPCM 8 bit unused
|
|
*
|
|
*/
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* BR0 - Base Register
|
|
* Ref: Section 10.3.1 on page 10-14
|
|
* OR0 - Option Register
|
|
* Ref: Section 10.3.2 on page 10-18
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
|
|
/* Bank 0,1 - FLASH SIMM
|
|
*
|
|
* This expects the FLASH SIMM to be connected to *CS0
|
|
* It consists of 4 AM29F016D parts.
|
|
*
|
|
* Note: For the 8 MB SIMM, *CS1 is unused.
|
|
*/
|
|
|
|
/* BR0 is configured as follows:
|
|
*
|
|
* - Base address of 0x40000000
|
|
* - 32 bit port size
|
|
* - Data errors checking is disabled
|
|
* - Read and write access
|
|
* - GPCM 60x bus
|
|
* - Access are handled by the memory controller according to MSEL
|
|
* - Not used for atomic operations
|
|
* - No data pipelining is done
|
|
* - Valid
|
|
*/
|
|
#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
|
|
BRx_PS_32 |\
|
|
BRx_MS_GPCM_P |\
|
|
BRx_V)
|
|
|
|
/* OR0 is configured as follows:
|
|
*
|
|
* - 8 MB
|
|
* - *BCTL0 is asserted upon access to the current memory bank
|
|
* - *CW / *WE are negated a quarter of a clock earlier
|
|
* - *CS is output at the same time as the address lines
|
|
* - Uses a clock cycle length of 5
|
|
* - *PSDVAL is generated internally by the memory controller
|
|
* unless *GTA is asserted earlier externally.
|
|
* - Relaxed timing is generated by the GPCM for accesses
|
|
* initiated to this memory region.
|
|
* - One idle clock is inserted between a read access from the
|
|
* current bank and the next access.
|
|
*/
|
|
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
|
|
ORxG_CSNT |\
|
|
ORxG_ACS_DIV1 |\
|
|
ORxG_SCY_5_CLK |\
|
|
ORxG_TRLX |\
|
|
ORxG_EHTR)
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* BR2 - Base Register
|
|
* Ref: Section 10.3.1 on page 10-14
|
|
* OR2 - Option Register
|
|
* Ref: Section 10.3.2 on page 10-16
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
|
|
/* Bank 2 - SDRAM DIMM
|
|
*
|
|
* 16MB DIMM: P/N
|
|
* 64MB DIMM: P/N 1W-8864X8-4-P1-EST or
|
|
* MT4LSDT864AG-10EB1 (Micron)
|
|
*
|
|
* Note: *CS3 is unused for this DIMM
|
|
*/
|
|
|
|
/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
|
|
*
|
|
* - Base address of 0x00000000
|
|
* - 64 bit port size (60x bus only)
|
|
* - Data errors checking is disabled
|
|
* - Read and write access
|
|
* - SDRAM 60x bus
|
|
* - Access are handled by the memory controller according to MSEL
|
|
* - Not used for atomic operations
|
|
* - No data pipelining is done
|
|
* - Valid
|
|
*/
|
|
#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
|
|
BRx_PS_64 |\
|
|
BRx_MS_SDRAM_P |\
|
|
BRx_V)
|
|
|
|
/* With a 16 MB DIMM, the OR2 is configured as follows:
|
|
*
|
|
* - 16 MB
|
|
* - 2 internal banks per device
|
|
* - Row start address bit is A9 with PSDMR[PBI] = 0
|
|
* - 11 row address lines
|
|
* - Back-to-back page mode
|
|
* - Internal bank interleaving within save device enabled
|
|
*/
|
|
#if (CONFIG_SYS_SDRAM0_SIZE == 16)
|
|
#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
|
|
ORxS_BPD_2 |\
|
|
ORxS_ROWST_PBI0_A9 |\
|
|
ORxS_NUMR_11)
|
|
|
|
/* With a 16 MB DIMM, the PSDMR is configured as follows:
|
|
*
|
|
* - Page Based Interleaving,
|
|
* - Refresh Enable,
|
|
* - Address Multiplexing where A5 is output on A14 pin
|
|
* (A6 on A15, and so on),
|
|
* - use address pins A16-A18 as bank select,
|
|
* - A9 is output on SDA10 during an ACTIVATE command,
|
|
* - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
|
|
* - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
|
|
* is 3 clocks,
|
|
* - earliest timing for READ/WRITE command after ACTIVATE command is
|
|
* 2 clocks,
|
|
* - earliest timing for PRECHARGE after last data was read is 1 clock,
|
|
* - earliest timing for PRECHARGE after last data was written is 1 clock,
|
|
* - CAS Latency is 2.
|
|
*/
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PSDMR - 60x Bus SDRAM Mode Register
|
|
* Ref: Section 10.3.3 on page 10-21
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
|
|
PSDMR_SDAM_A14_IS_A5 |\
|
|
PSDMR_BSMA_A16_A18 |\
|
|
PSDMR_SDA10_PBI0_A9 |\
|
|
PSDMR_RFRC_7_CLK |\
|
|
PSDMR_PRETOACT_3W |\
|
|
PSDMR_ACTTORW_2W |\
|
|
PSDMR_LDOTOPRE_1C |\
|
|
PSDMR_WRC_1C |\
|
|
PSDMR_CL_2)
|
|
#endif /* (CONFIG_SYS_SDRAM0_SIZE == 16) */
|
|
|
|
/* With a 64 MB DIMM, the OR2 is configured as follows:
|
|
*
|
|
* - 64 MB
|
|
* - 4 internal banks per device
|
|
* - Row start address bit is A8 with PSDMR[PBI] = 0
|
|
* - 12 row address lines
|
|
* - Back-to-back page mode
|
|
* - Internal bank interleaving within save device enabled
|
|
*/
|
|
#if (CONFIG_SYS_SDRAM0_SIZE == 64)
|
|
#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
|
|
ORxS_BPD_4 |\
|
|
ORxS_ROWST_PBI0_A8 |\
|
|
ORxS_NUMR_12)
|
|
|
|
/* With a 64 MB DIMM, the PSDMR is configured as follows:
|
|
*
|
|
* - Page Based Interleaving,
|
|
* - Refresh Enable,
|
|
* - Address Multiplexing where A5 is output on A14 pin
|
|
* (A6 on A15, and so on),
|
|
* - use address pins A14-A16 as bank select,
|
|
* - A9 is output on SDA10 during an ACTIVATE command,
|
|
* - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
|
|
* - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
|
|
* is 3 clocks,
|
|
* - earliest timing for READ/WRITE command after ACTIVATE command is
|
|
* 2 clocks,
|
|
* - earliest timing for PRECHARGE after last data was read is 1 clock,
|
|
* - earliest timing for PRECHARGE after last data was written is 1 clock,
|
|
* - CAS Latency is 2.
|
|
*/
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PSDMR - 60x Bus SDRAM Mode Register
|
|
* Ref: Section 10.3.3 on page 10-21
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
|
|
PSDMR_SDAM_A14_IS_A5 |\
|
|
PSDMR_BSMA_A14_A16 |\
|
|
PSDMR_SDA10_PBI0_A9 |\
|
|
PSDMR_RFRC_7_CLK |\
|
|
PSDMR_PRETOACT_3W |\
|
|
PSDMR_ACTTORW_2W |\
|
|
PSDMR_LDOTOPRE_1C |\
|
|
PSDMR_WRC_1C |\
|
|
PSDMR_CL_2)
|
|
#endif /* (CONFIG_SYS_SDRAM0_SIZE == 64) */
|
|
|
|
#define CONFIG_SYS_PSRT 0x0e
|
|
#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
|
|
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* BR4 - Base Register
|
|
* Ref: Section 10.3.1 on page 10-14
|
|
* OR4 - Option Register
|
|
* Ref: Section 10.3.2 on page 10-18
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
/* Bank 4 - Onboard Memory Mapped IO controller
|
|
*
|
|
* This expects the onboard IO controller to connected to *CS4 and
|
|
* the local bus.
|
|
* - Base address of 0xe0000000
|
|
* - 8 bit port size (local bus only)
|
|
* - Read and write access
|
|
* - GPCM local bus
|
|
* - Not used for atomic operations
|
|
* - No data pipelining is done
|
|
* - Valid
|
|
* - extended hold time
|
|
* - 11 wait states
|
|
*/
|
|
|
|
#ifdef CONFIG_SYS_IO_BASE
|
|
# define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
|
|
BRx_PS_8 |\
|
|
BRx_MS_GPCM_L |\
|
|
BRx_V)
|
|
|
|
# define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
|
|
ORxG_SCY_11_CLK |\
|
|
ORxG_EHTR)
|
|
#endif /* CONFIG_SYS_IO_BASE */
|
|
#endif /* __CONFIG_H */
|