mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
d98b0523cf
Now that warm booting is not supported, there isn't a need for the BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them. Note that this change makes the board info bd_bootflags field useless. It will always be set to 0, but we leave it around so that we don't break the board info structure that some OSes are expecting to be passed from U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
423 lines
15 KiB
C
423 lines
15 KiB
C
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
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#define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */
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#define CONFIG_SYS_TEXT_BASE 0xFF000000
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#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 115200
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
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"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
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"nfsaddrs=10.0.0.99:10.0.0.2"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_IDE
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#undef CONFIG_CMD_SAVEENV
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#undef CONFIG_CMD_FLASH
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*----------------------------------------------------------------------*/
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#define CONFIG_ETHADDR 00:D0:93:00:01:CB
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#define CONFIG_IPADDR 10.0.0.98
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#define CONFIG_SERVERIP 10.0.0.1
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#undef CONFIG_BOOTCOMMAND
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#define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000"
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/*----------------------------------------------------------------------*/
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
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#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
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#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFF000000
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#ifdef DEBUG
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#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
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#else
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#endif
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 0 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 0 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
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#define CONFIG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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/* 0x00000040 */
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#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit, set PLL multiplication factor !
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*/
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/* 0x00b0c0c0 */
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#define CONFIG_SYS_PLPRCR \
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( (11 << PLPRCR_MF_SHIFT) | \
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PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
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/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
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PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
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)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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/* 0x01800014 */
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#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
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SCCR_RTDIV | SCCR_RTSEL | \
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/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
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SCCR_EBDF00 | SCCR_DFSYNC00 | \
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SCCR_DFBRG00 | SCCR_DFNL000 | \
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SCCR_DFNH000 | SCCR_DFLCD101 | \
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SCCR_DFALCD00)
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register
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*-----------------------------------------------------------------------
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*/
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/* 0x00C3 */
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#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration Register
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*-----------------------------------------------------------------------
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*/
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/* TIMEP=2 */
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#define CONFIG_SYS_RCCR 0x0200
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/*-----------------------------------------------------------------------
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* RMDS - RISC Microcode Development Support Control Register
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RMDS 0
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/*-----------------------------------------------------------------------
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* SDSR - SDMA Status Register
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_SDSR ((u_char)0x83)
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/*-----------------------------------------------------------------------
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* SDMR - SDMA Mask Register
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_SDMR ((u_char)0x00)
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/*-----------------------------------------------------------------------
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*
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* Interrupt Levels
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
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#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
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#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
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#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
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#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
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#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
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#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
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#define CONFIG_IDE_LED 1 /* LED for ide supported */
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#define CONFIG_IDE_RESET 1 /* reset for ide supported */
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#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
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#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
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#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00
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#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
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#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_SYS_DER 0
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any)
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* but not too much to meddle with FLASH accesses
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*/
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/* EPROMs are 512kb */
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#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
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#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
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/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
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#define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
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OR_SCY_5_CLK | OR_EHTR)
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#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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/* 16 bit, bank valid */
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#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
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#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
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/* 16 bit, bank valid */
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#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
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/*
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* BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC)
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*
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*/
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#define SRAM_BASE 0xFE200000 /* SRAM bank */
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#define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */
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#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
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#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
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#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
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#define PER8_BASE 0xFE000000 /* PER8 bank */
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#define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */
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#define SHARC_BASE 0xFE400000 /* SHARC bank */
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#define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */
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/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
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#define CONFIG_SYS_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */
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#define CONFIG_SYS_OR2 (SRAM_OR_AM | CONFIG_SYS_OR_TIMING_SRAM )
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#define CONFIG_SYS_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
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#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */
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#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
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#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
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#define CONFIG_SYS_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */
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#define CONFIG_SYS_OR4 (PER8_OR_AM | CONFIG_SYS_OR_TIMING_PER8 )
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#define CONFIG_SYS_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
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#define CONFIG_SYS_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */
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#define CONFIG_SYS_OR5 (SHARC_OR_AM | CONFIG_SYS_OR_TIMING_SHARC )
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#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
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/*
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* Memory Periodic Timer Prescaler
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*/
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/* periodic timer for refresh */
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#define CONFIG_SYS_MBMR_PTB 204
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/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
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#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
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#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
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/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
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#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
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#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
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/*
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* MBMR settings for SDRAM
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*/
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/* 8 column SDRAM */
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#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
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MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
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MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
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#endif /* __CONFIG_H */
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