mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
d98b0523cf
Now that warm booting is not supported, there isn't a need for the BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them. Note that this change makes the board info bd_bootflags field useless. It will always be set to 0, but we leave it around so that we don't break the board info structure that some OSes are expecting to be passed from U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
407 lines
15 KiB
C
407 lines
15 KiB
C
/*
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* (C) Copyright 2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405EP 1 /* This is a PPC405 CPU */
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_G2000 1 /* ...on a PLU405 board */
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#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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#if 0 /* test-only */
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#define CONFIG_BAUDRATE 115200
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#else
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#define CONFIG_BAUDRATE 9600
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#endif
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#define CONFIG_PREBOOT
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off\0" \
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"addmisc=setenv bootargs ${bootargs} " \
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"console=ttyS0,${baudrate} " \
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"panic=1\0" \
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"flash_nfs=run nfsargs addip addmisc;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addmisc;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};" \
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"run nfsargs addip addmisc;bootm\0" \
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"rootpath=/opt/eldk/ppc_4xx\0" \
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"bootfile=/tftpboot/g2000/pImage\0" \
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"kernel_addr=ff800000\0" \
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"ramdisk_addr=ff900000\0" \
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"pciconfighost=yes\0" \
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""
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#define CONFIG_BOOTCOMMAND "run net_nfs"
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_PHY1_ADDR 1 /* PHY address */
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#if 0 /* test-only */
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#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_EEPROM
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#if 0 /* test-only */
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#endif
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
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#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
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#define CONFIG_SYS_BASE_BAUD 691200
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/* The following table includes the supported baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 }
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
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/*----------------------------------------------------------------------------*/
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/* adding Ethernet setting: FTS OUI 00:11:0B */
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/*----------------------------------------------------------------------------*/
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#define CONFIG_ETHADDR 00:11:0B:00:00:01
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#define CONFIG_HAS_ETH1
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#define CONFIG_ETH1ADDR 00:11:0B:00:00:02
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#define CONFIG_IPADDR 10.48.8.178
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#define CONFIG_IP1ADDR 10.48.8.188
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#define CONFIG_NETMASK 255.255.255.128
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#define CONFIG_SERVERIP 10.48.8.138
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/*-----------------------------------------------------------------------
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* RTC stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_RTC_DS1337
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#if 0 /* test-only */
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/*-----------------------------------------------------------------------
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* NAND-FLASH stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
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#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
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#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
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#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
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#endif
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
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#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
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#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
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#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
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#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#if 0 /* APC405 */
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* test-only...*/
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#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* test-only */
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#else /* G2000 */
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* test-only...*/
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#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* test-only */
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#endif
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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/*-----------------------------------------------------------------------
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* Environment Variable setup
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*/
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#if 1 /* test-only */
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#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
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#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
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/* total size of a CAT24WC16 is 2048 bytes */
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#else /* DEFAULT: environment in flash, using redundand flash sectors */
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#define CONFIG_ENV_ADDR 0xFFFA0000 /* environment starts before u-boot */
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k bytes may be used for env vars*/
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#endif
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/*-----------------------------------------------------------------------
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* I2C EEPROM (CAT24WC16) for environment
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*/
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#define CONFIG_HARD_I2C /* I2c with hardware support */
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#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
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/* CAT24WC08/16... */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
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/* 16 byte page write mode using*/
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/* last 4 bits of the address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*/
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/* Memory Bank 0 (Intel Strata Flash) initialization */
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#define CONFIG_SYS_EBC_PB0AP 0x92015480
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#define CONFIG_SYS_EBC_PB0CR 0xFF87A000 /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
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/* Memory Bank 1 ( Power TAU) initialization */
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/* #define CONFIG_SYS_EBC_PB1AP 0x04041000 */
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/* #define CONFIG_SYS_EBC_PB1CR 0xF0018000 */ /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
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#define CONFIG_SYS_EBC_PB1AP 0x00000000
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#define CONFIG_SYS_EBC_PB1CR 0x00000000
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/* Memory Bank 2 (Intel Flash) initialization */
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#define CONFIG_SYS_EBC_PB2AP 0x00000000
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#define CONFIG_SYS_EBC_PB2CR 0x00000000
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/* Memory Bank 3 (NAND) initialization */
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#define CONFIG_SYS_EBC_PB3AP 0x92015480
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#define CONFIG_SYS_EBC_PB3CR 0xF40B8000 /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
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/* Memory Bank 4 (FPGA regs) initialization */
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#define CONFIG_SYS_EBC_PB4AP 0x00000000
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#define CONFIG_SYS_EBC_PB4CR 0x00000000 /* leave it blank */
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#define CONFIG_SYS_NAND_BASE 0xF4000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
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#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
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#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Definitions for GPIO setup (PPC405EP specific)
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*
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* GPIO0[0] - External Bus Controller BLAST output
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* GPIO0[1-9] - Instruction trace outputs
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* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
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* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
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* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
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* GPIO0[24-27] - UART0 control signal inputs/outputs
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* GPIO0[28-29] - UART1 data signal input/output
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* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
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*
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* following GPIO setting changed for G20000, 080304
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*/
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#define CONFIG_SYS_GPIO0_OSRL 0x40005555
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#define CONFIG_SYS_GPIO0_OSRH 0x40000110
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#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
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#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
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#define CONFIG_SYS_GPIO0_TSRL 0x00000000
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#define CONFIG_SYS_GPIO0_TSRH 0x00000000
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#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
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/*
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* Default speed selection (cpu_plb_opb_ebc) in mhz.
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* This value will be set if iic boot eprom is disabled.
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*/
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#if 1
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#define PLLMR0_DEFAULT PLLMR0_266_66_33_33
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#define PLLMR1_DEFAULT PLLMR1_266_66_33_33
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#endif
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#if 0
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#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
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#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
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#endif
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#if 0
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#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
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#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
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#endif
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#if 0
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#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
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#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
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#endif
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#endif /* __CONFIG_H */
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