Dave Liu 3e731aaba3 fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave ... In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2010-01-05 13:50:07 -06:00
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common_timing_params.h	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00
ctrl_regs.c	fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave	2010-01-05 13:50:07 -06:00
ddr1_dimm_params.c	fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT	2009-06-12 09:15:50 -05:00
ddr2_dimm_params.c	fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT	2009-06-12 09:15:50 -05:00
ddr3_dimm_params.c	ppc/8xxx: Misc DDR related fixes	2009-09-15 21:30:08 -05:00
ddr.h	fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT	2009-06-12 09:15:50 -05:00
lc_common_dimm_params.c	fsl-ddr: add the DDR3 SPD infrastructure	2009-03-30 13:33:50 -05:00
main.c	85xx, 86xx: Add common board_add_ram_info()	2009-07-22 09:43:48 -05:00
Makefile	fsl-ddr: add the DDR3 SPD infrastructure	2009-03-30 13:33:50 -05:00
options.c	fsl-ddr: add the override for write leveling	2010-01-05 13:49:10 -06:00
util.c	mpc8xxx: improve LAW error messages when setting up DDR	2009-10-16 10:21:39 -05:00