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![Neil Armstrong](/assets/img/avatar_default.png)
This adds video output support for Amlogic GXBB/GXL/GXM chips. The supported ports are CVBS and HDMI (based on DW_HDMI). When using HDMI, only DMT modes are supported. There is support for simple-framebuffer (CONFIG_VIDEO_DT_SIMPLEFB) Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jorge Ramire-Ortiz <jramirez@baylibre.com> Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> [narmstrong: fixed defines alignment in meson_canvas.c] Reviewed-by: Anatolij Gustschin <agust@denx.de>
212 lines
5.1 KiB
C
212 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Amlogic Meson Video Processing Unit driver
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*
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* Copyright (c) 2018 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include "meson_vpu.h"
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#include <power-domain.h>
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#include <efi_loader.h>
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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#include <fdt_support.h>
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#include <linux/sizes.h>
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#include <asm/arch/mem.h>
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#include "meson_registers.h"
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#include "simplefb_common.h"
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#define MESON_VPU_OVERSCAN SZ_64K
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/* Static variable for use in meson_vpu_rsv_fb() */
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static struct meson_framebuffer {
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u64 base;
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u64 fb_size;
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unsigned int xsize;
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unsigned int ysize;
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bool is_cvbs;
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} meson_fb = { 0 };
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static int meson_vpu_setup_mode(struct udevice *dev, struct udevice *disp)
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{
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struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct display_timing timing;
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bool is_cvbs = false;
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int ret = 0;
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if (disp) {
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ret = display_read_timing(disp, &timing);
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if (ret) {
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debug("%s: Failed to read timings\n", __func__);
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goto cvbs;
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}
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uc_priv->xsize = timing.hactive.typ;
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uc_priv->ysize = timing.vactive.typ;
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ret = display_enable(disp, 0, &timing);
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if (ret)
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goto cvbs;
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} else {
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cvbs:
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/* CVBS has a fixed 720x480i (NTSC) and 720x576i (PAL) */
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is_cvbs = true;
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timing.flags = DISPLAY_FLAGS_INTERLACED;
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uc_priv->xsize = 720;
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uc_priv->ysize = 576;
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}
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uc_priv->bpix = VPU_MAX_LOG2_BPP;
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meson_fb.is_cvbs = is_cvbs;
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meson_fb.xsize = uc_priv->xsize;
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meson_fb.ysize = uc_priv->ysize;
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/* Move the framebuffer to the end of addressable ram */
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meson_fb.fb_size = ALIGN(meson_fb.xsize * meson_fb.ysize *
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((1 << VPU_MAX_LOG2_BPP) / 8) +
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MESON_VPU_OVERSCAN, EFI_PAGE_SIZE);
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meson_fb.base = gd->bd->bi_dram[0].start +
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gd->bd->bi_dram[0].size - meson_fb.fb_size;
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/* Override the framebuffer address */
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uc_plat->base = meson_fb.base;
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meson_vpu_setup_plane(dev, timing.flags & DISPLAY_FLAGS_INTERLACED);
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meson_vpu_setup_venc(dev, &timing, is_cvbs);
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meson_vpu_setup_vclk(dev, &timing, is_cvbs);
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video_set_flush_dcache(dev, 1);
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return 0;
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}
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static const struct udevice_id meson_vpu_ids[] = {
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{ .compatible = "amlogic,meson-gxbb-vpu", .data = VPU_COMPATIBLE_GXBB },
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{ .compatible = "amlogic,meson-gxl-vpu", .data = VPU_COMPATIBLE_GXL },
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{ .compatible = "amlogic,meson-gxm-vpu", .data = VPU_COMPATIBLE_GXM },
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{ }
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};
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static int meson_vpu_probe(struct udevice *dev)
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{
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struct meson_vpu_priv *priv = dev_get_priv(dev);
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struct power_domain pd;
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struct udevice *disp;
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int ret;
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/* Before relocation we don't need to do anything */
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if (!(gd->flags & GD_FLG_RELOC))
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return 0;
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priv->dev = dev;
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priv->io_base = dev_remap_addr_index(dev, 0);
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if (!priv->io_base)
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return -EINVAL;
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priv->hhi_base = dev_remap_addr_index(dev, 1);
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if (!priv->hhi_base)
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return -EINVAL;
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priv->dmc_base = dev_remap_addr_index(dev, 2);
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if (!priv->dmc_base)
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return -EINVAL;
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ret = power_domain_get(dev, &pd);
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if (ret)
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return ret;
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ret = power_domain_on(&pd);
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if (ret)
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return ret;
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meson_vpu_init(dev);
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/* probe the display */
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ret = uclass_get_device(UCLASS_DISPLAY, 0, &disp);
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return meson_vpu_setup_mode(dev, ret ? NULL : disp);
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}
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static int meson_vpu_bind(struct udevice *dev)
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{
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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plat->size = VPU_MAX_WIDTH * VPU_MAX_HEIGHT *
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(1 << VPU_MAX_LOG2_BPP) / 8;
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return 0;
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}
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#if defined(CONFIG_VIDEO_DT_SIMPLEFB)
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static void meson_vpu_setup_simplefb(void *fdt)
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{
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const char *pipeline = NULL;
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u64 mem_start, mem_size;
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int offset, ret;
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if (meson_fb.is_cvbs)
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pipeline = "vpu-cvbs";
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else
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pipeline = "vpu-hdmi";
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offset = meson_simplefb_fdt_match(fdt, pipeline);
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if (offset < 0) {
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eprintf("Cannot setup simplefb: node not found\n");
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/* If simplefb is missing, add it as reserved memory */
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meson_board_add_reserved_memory(fdt, meson_fb.base,
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meson_fb.fb_size);
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return;
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}
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/*
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* SimpleFB will try to iomap the framebuffer, so we can't use
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* fdt_add_mem_rsv on the memory area. Instead, the FB is stored
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* at the end of the RAM and we strip this portion from the kernel
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* allowed region
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*/
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mem_start = gd->bd->bi_dram[0].start;
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mem_size = gd->bd->bi_dram[0].size - meson_fb.fb_size;
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ret = fdt_fixup_memory_banks(fdt, &mem_start, &mem_size, 1);
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if (ret) {
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eprintf("Cannot setup simplefb: Error reserving memory\n");
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return;
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}
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ret = fdt_setup_simplefb_node(fdt, offset, meson_fb.base,
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meson_fb.xsize, meson_fb.ysize,
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meson_fb.xsize * 4, "x8r8g8b8");
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if (ret)
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eprintf("Cannot setup simplefb: Error setting properties\n");
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}
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#endif
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void meson_vpu_rsv_fb(void *fdt)
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{
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if (!meson_fb.base || !meson_fb.xsize || !meson_fb.ysize)
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return;
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#if defined(CONFIG_EFI_LOADER)
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efi_add_memory_map(meson_fb.base, meson_fb.fb_size >> EFI_PAGE_SHIFT,
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EFI_RESERVED_MEMORY_TYPE, false);
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#endif
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#if defined(CONFIG_VIDEO_DT_SIMPLEFB)
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meson_vpu_setup_simplefb(fdt);
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#endif
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}
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U_BOOT_DRIVER(meson_vpu) = {
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.name = "meson_vpu",
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.id = UCLASS_VIDEO,
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.of_match = meson_vpu_ids,
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.probe = meson_vpu_probe,
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.bind = meson_vpu_bind,
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.priv_auto_alloc_size = sizeof(struct meson_vpu_priv),
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.flags = DM_FLAG_PRE_RELOC,
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};
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