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https://github.com/brain-hackers/u-boot-brain
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![Mingkai Hu](/assets/img/avatar_default.png)
There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
151 lines
2.8 KiB
C
151 lines
2.8 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <fsl_ifc.h>
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#include <fsl_ddr.h>
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#include <asm/io.h>
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#include <fdt_support.h>
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#include <libfdt.h>
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#include <fsl_debug_server.h>
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#include <fsl-mc/fsl_mc.h>
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#include <environment.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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init_final_memctl_regs();
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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return 0;
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}
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int board_early_init_f(void)
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{
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fsl_lsch3_early_init_f();
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return 0;
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}
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void detail_board_ddr_info(void)
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{
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puts("\nDDR ");
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print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
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print_ddr_info(0);
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if (gd->bd->bi_dram[2].size) {
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puts("\nDP-DDR ");
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print_size(gd->bd->bi_dram[2].size, "");
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print_ddr_info(CONFIG_DP_DDR_CTRL);
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}
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}
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int dram_init(void)
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{
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gd->ram_size = initdram(0);
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return 0;
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}
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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#ifdef CONFIG_FSL_DEBUG_SERVER
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debug_server_init();
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#endif
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return 0;
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}
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#endif
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unsigned long get_dram_size_to_hide(void)
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{
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unsigned long dram_to_hide = 0;
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/* Carve the Debug Server private DRAM block from the end of DRAM */
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#ifdef CONFIG_FSL_DEBUG_SERVER
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dram_to_hide += debug_server_get_dram_block_size();
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#endif
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/* Carve the MC private DRAM block from the end of DRAM */
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#ifdef CONFIG_FSL_MC_ENET
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dram_to_hide += mc_get_dram_block_size();
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#endif
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return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
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}
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int board_eth_init(bd_t *bis)
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{
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int error = 0;
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#ifdef CONFIG_SMC91111
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error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
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#endif
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#ifdef CONFIG_FSL_MC_ENET
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error = cpu_eth_init(bis);
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#endif
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return error;
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}
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#ifdef CONFIG_FSL_MC_ENET
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void fdt_fixup_board_enet(void *fdt)
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{
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int offset;
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offset = fdt_path_offset(fdt, "/fsl-mc");
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/*
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* TODO: Remove this when backward compatibility
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* with old DT node (fsl,dprc@0) is no longer needed.
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*/
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if (offset < 0)
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offset = fdt_path_offset(fdt, "/fsl,dprc@0");
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if (offset < 0) {
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printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
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__func__, offset);
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return;
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}
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if (get_mc_boot_status() == 0)
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fdt_status_okay(fdt, offset);
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else
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fdt_status_fail(fdt, offset);
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}
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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ft_cpu_setup(blob, bd);
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/* fixup DT for the two GPP DDR banks */
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base[0] = gd->bd->bi_dram[0].start;
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size[0] = gd->bd->bi_dram[0].size;
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base[1] = gd->bd->bi_dram[1].start;
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size[1] = gd->bd->bi_dram[1].size;
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fdt_fixup_memory_banks(blob, base, size, 2);
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#ifdef CONFIG_FSL_MC_ENET
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fdt_fixup_board_enet(blob);
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fsl_mc_ldpaa_exit(bd);
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#endif
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return 0;
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}
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#endif
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